公开(公告)号：US11558113B2

公开(公告)日：2023-01-17

申请号：US17040002

申请日：2019-02-05

Applicant: Xieon Networks S.A.R.L.

Inventor： Stefano Calabrò ,  Lutz Rapp ,  Bernhard Spinnler

IPC: H04B10/07 ,  H04B17/00 ,  H04B10/079 ,  H04B10/40 ,  H04B10/50 ,  H04B10/61

Abstract: Disclosed herein is a transponder comprising a transmitter and a receiver. The transponder further comprises a receiver input amplifier, a bypass line, and a control unit configured for determining the performance of the transponder in relation to an OSNR related parameter, by controlling the transponder to generate a noise signal to be received by the receiver. The receiver input amplifier is operated to thereby cause ASE in the receiver input amplifier to facilitate the determination. A test signal is generated at the transmitter Said noise signal and said test signal, and/or one or more respective replicas thereof, are superimposed to form a combined signal to be received by said receiver to further facilitate determination of said performance related parameter based on said combined signal, wherein for generating said combined signal, said test signal is fed from the transmitter to the receiver by means of said bypass line.

公开(公告)号：US11139834B2

公开(公告)日：2021-10-05

申请号：US16092813

申请日：2017-04-13

Applicant: Xieon Networks S.a.r.l.

Inventor： Stefano Calabrò

IPC: H03M13/11 ,  H03M13/00

Abstract: Disclosed herein is a decoder 10 for decoding a family of L rate compatible parity check codes, said family of parity check codes comprising a first code that can be represented by a bipartite graph having variable nodes, check nodes, and edges, and L−1 codes of increasingly lower code rate, among which the i-th code can be represented by a bipartite graph corresponding to the bipartite graph representing the (i−1)-th code, to which an equal number of ni variable nodes and check nodes are added, wherein the added check nodes are connected via edges with selected ones of the variable nodes included in said i-th code, while the added variable nodes are connected via edges with selected added check nodes only. The decoder comprising L check node processing units 14, among which the i-th check node processing unit processes only the check nodes added in the i-th code over the (i−1)-th code, wherein said L check node processing units 14 are configured to operate in parallel.