公开(公告)号：US11055458B1

公开(公告)日：2021-07-06

申请号：US16899092

申请日：2020-06-11

Applicant: Xilinx, Inc.

Inventor： Aparna Suresh ,  Tapodyuti Mandal ,  Vinayak Thonda

IPC: G06F30/00 ,  G06F30/3308 ,  G01R31/3183 ,  G06F117/08

Abstract: Verification for a design can include, for a covergroup corresponding to a variable of the design, generating a state coverage data structure specifying a plurality of transition bins. Each transition bin can include a sequence. Each sequence can specify states of the variable to be traversed in order during simulation of the design. Verification can include generating a state sequence table configured to use state values as keys and one or more of the sequences as data for the respective keys, and during simulation of the design, maintaining a sequence list specifying each sequence that is running based on sample values of the variable. Hit counts for the transition bins can be updated during the simulation.