公开(公告)号：US20160277019A1

公开(公告)日：2016-09-22

申请号：US14659747

申请日：2015-03-17

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings ,  Chandrika Durbha

IPC: H03K17/16 ,  H03K3/012

CPC classification number: H03K17/161 ,  H03K3/012 ,  H03K17/063 ,  H03K17/165 ,  H03K2217/0054

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.

Abstract translation: 在一个示例中，一种装置包括具有与开关输入和开关输出之间的p型金属氧化物半导体（PMOS）电路并联的n型金属氧化物半导体（NMOS）电路的模拟开关。 模拟开关响应于确定其开关状态的使能信号。 NMOS电路包括耦合到缓冲器N沟道晶体管的开关N沟道晶体管，耦合到使能信号的开关N沟道晶体管的栅极和耦合到调制N沟道的缓冲器N沟道晶体管的栅极 栅极电压。 PMOS电路包括耦合到缓冲器P沟道晶体管的开关P沟道晶体管，耦合到使能信号的补码的开关P沟道晶体管的栅极和耦合到调制的P沟道晶体管的缓冲器P沟道晶体管的栅极 P沟道栅极电压。 控制电路耦合到模拟开关以提供调制的N沟道和调制的P沟道栅极电压，其中每个沟道栅极电压基于开关状态在相应的电源电压和相应的栅极感应漏极泄漏（GIDL）缓解电压之间交替。

公开(公告)号：US10236873B2

公开(公告)日：2019-03-19

申请号：US14659747

申请日：2015-03-17

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings ,  Chandrika Durbha

IPC: H03K17/16 ,  H03K17/06 ,  H03K3/012

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.