公开(公告)号：US09639640B1

公开(公告)日：2017-05-02

申请号：US14693506

申请日：2015-04-22

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Robert M. Ondris ,  Chiao K. Hwang

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5027 ,  G06F17/5054 ,  G06F2217/62 ,  G06F2217/84

Abstract: An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that include the selected circuit elements. The programmable IC is configured with the configuration data, and the programmable IC as configured with the respective ring oscillator circuits is operated. Respective delay values of the selected circuit elements are determined from output of the ring oscillator circuits. The delay values are stored in association with identifiers of the selected circuit elements in a memory arrangement.

公开(公告)号：US10289784B1

公开(公告)日：2019-05-14

申请号：US15432537

申请日：2017-02-14

Applicant: Xilinx, Inc.

Inventor： Chiao K. Hwang ,  Zicheng G. Ling ,  Nagaraj Savithri

IPC: G06F17/50

Abstract: The disclosed approaches process a circuit design that specifies a clock signal. A plurality of wire segments of an integrated circuit (IC) are selected for a clock path to carry the clock signal. A delay of the clock path is determined based on delay values associated with identifiers of the wire segments and variation factors. Configuration data is generated from the circuit design once the delay of the clock path satisfies a timing constraint, and a circuit is generated from the configuration data to implement a circuit according to the circuit design.