公开(公告)号：US10430540B1

公开(公告)日：2019-10-01

申请号：US15880429

申请日：2018-01-25

Applicant: Xilinx, Inc.

Inventor： David Van Campenhout

IPC: G06F17/50 ,  G06F8/41

Abstract: Disclosed approaches include inputting a block diagram representation of a circuit design to a processor. Respective high-level programming language (HLL) code fragments associated with each block of the block diagram representation are determined. A dependency graph is generated from the block diagram representation. One or more clusters of vertices are generated from the dependency graph. Each of the HLL code fragments represented by the vertices of each cluster includes a for-loop, and each cluster includes a subset of the plurality of vertices and edges. For each of the clusters, a plurality of for-loops of the HLL code fragments associated with blocks represented by the vertices of the cluster are combined into a single for-loop. An HLL function is generated from each single for-loop and the HLL code fragments associated with each block that is not represented by any of the one or more clusters.

公开(公告)号：US10706193B1

公开(公告)日：2020-07-07

申请号：US16209724

申请日：2018-12-04

Applicant: Xilinx, Inc.

Inventor： David Van Campenhout ,  Avinash Somalinga Suresh ,  Ali Behboodian

IPC: G06F30/30 ,  G06F30/33 ,  G06F30/392

Abstract: Approaches for simulating and processing a circuit design involve recognizing by a design processing tool a replaceable subsystem in a circuit design having multiple blocks. The replaceable subsystem includes a subset of the blocks. The design tool converts the subset of blocks into an executable program and schedules activation of blocks of the circuit design other than the subset of blocks during simulation of the circuit design. The scheduled blocks are activated during simulation according to the scheduling, and activation of the subset of the plurality of blocks is bypassed during simulation with a call to the executable program.