Data mover circuitry for N-dimensional data in an integrated circuit

    公开(公告)号:US11327677B1

    公开(公告)日:2022-05-10

    申请号:US17019454

    申请日:2020-09-14

    Applicant: Xilinx, Inc.

    Abstract: An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.

    CIRCULAR BUFFER ARCHITECTURE USING LOCAL MEMORIES WITH LIMITED RESOURCES

    公开(公告)号:US20230205452A1

    公开(公告)日:2023-06-29

    申请号:US17646172

    申请日:2021-12-28

    Applicant: Xilinx, Inc.

    CPC classification number: G06F3/0656 G06F3/0604 G06F3/0679

    Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

    Circular buffer architecture using local memories with limited resources

    公开(公告)号:US11954359B2

    公开(公告)日:2024-04-09

    申请号:US17646172

    申请日:2021-12-28

    Applicant: Xilinx, Inc.

    CPC classification number: G06F3/0656 G06F3/0604 G06F3/0679

    Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

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