公开(公告)号：US20240046015A1

公开(公告)日：2024-02-08

申请号：US17818341

申请日：2022-08-08

Applicant: Xilinx, Inc.

Inventor： Krishnam Tibrewala

IPC: G06F30/3308 ,  G06F30/3323

CPC classification number: G06F30/3308 ,  G06F30/3323

Abstract: Providing first-in-first-out (FIFO) memory guidance for a multi-processor computing architecture includes compiling a design for a data processing array to generate a compiled design. The compiled design is mapped and routed to the data processing array. The compiled design is simulated using a modified device model of the data processing array. The modified device model uses infinite FIFO models. FIFO memory usage data is generated by tracking amounts of data stored in the infinite FIFO memory models during runtime of the simulation of the compiled design. FIFO memory requirements for one or more nets of the design are determined from the FIFO memory usage data and the compiled design.