公开(公告)号：US10523596B1

公开(公告)日：2019-12-31

申请号：US14616587

申请日：2015-02-06

Applicant: Xilinx, Inc.

Inventor： Max Ferger ,  Michaela Blott

IPC: H04L12/935

Abstract: A circuit for merging streams of data to generate sorted output data is described. The circuit comprises a first input coupled to receive a first data stream having a first set of N values; a second input coupled to receive a second data stream having second set of N values; a routing circuit coupled to the first input and the second input, the routing circuit enabling the routing of the first set of N values of the first data stream and the second set of N values of the second data stream; and a comparator circuit coupled to receive each value of the first set of N values and the second set of N values from the routing circuit, the comparator circuit having N comparators, wherein each comparator of the N comparators is coupled to receive a value of the first set of N values and a value of the second set of N values. A method of merging streams of data is also disclosed.