公开(公告)号：US11144235B1

公开(公告)日：2021-10-12

申请号：US16534527

申请日：2019-08-07

Applicant: Xilinx, Inc.

Inventor： Rowan Lyons ,  Noel Brady

IPC: G06F3/06 ,  G06F11/26

Abstract: Disclosed approaches for measuring memory performance include inputting respective sets of parameter values for master circuits. Each set specifies control over a transaction issuance rate, a transaction size, or an address pattern. Configuration data is generated for implementing master circuits in programmable logic circuitry based on the sets of parameter values. Each master circuit is configured to issue memory transactions according to the respective set of parameter values. The programmable logic circuitry is configured with the configuration data, and the master circuits are activated. Each master circuit issues memory transactions based on the respective set of parameter values. Each master circuit measures performance metrics of memory circuitry in processing the memory transactions and stores data indicative of the performance metrics.