公开(公告)号：US10318699B1

公开(公告)日：2019-06-11

申请号：US15621913

申请日：2017-06-13

Applicant: Xilinx, Inc.

Inventor： Satish B. Sivaswamy ,  Parivallal Kannan

IPC: G06F17/50

Abstract: Disclosed approaches for fixing a hold time violation in a circuit design include determining a first hold budget that is an amount to fix a first hold time violation on a first path of the circuit design. For each connection of a first plurality of connections on the first path, a respective projected setup slack of the connection in allocating the first hold budget to fixing the first hold time violation on the connection is determined. For each connection of the first plurality of connections, a respective connection hold budget based on the first hold budget and the respective projected setup slack is determined. Each connection of the first plurality of connections is adjusted according to the respective connection hold budget.

公开(公告)号：US10416232B1

公开(公告)日：2019-09-17

申请号：US16012535

申请日：2018-06-19

Applicant: Xilinx, Inc.

Inventor： Guenter Stenz ,  Parivallal Kannan

IPC: G01R31/317 ,  G01R31/3183 ,  H03K19/177 ,  G01R31/3185 ,  G11C29/00

Abstract: Implementing a circuit design may include detecting, using computer hardware, a net of the circuit design with a hold timing violation, generating, using the computer hardware, a list including each load of the net, and filtering, using the computer hardware, the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing. Using the computer hardware, the circuit design is modified by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point.