公开(公告)号：US10754760B1

公开(公告)日：2020-08-25

申请号：US15982698

申请日：2018-05-17

Applicant: Xilinx, Inc.

Inventor： Paul S. Levy ,  Giulio Corradi

IPC: G06F11/36 ,  G01R31/317

Abstract: Disclosed approaches involve at least one processor executing a program and a debug interface circuit coupled to the processor. The debug interface circuit is configured to transmit first trace data from the first processor. A debug access port is coupled to the debug interface circuit. A fault detection circuit is coupled to the debug access port and is configured to receive the first trace data via the debug access port and compare the first trace data to second data. The fault detection circuit generates an error signal to the first processor in response to a discrepancy between the first trace data and the second data.