公开(公告)号：US10664561B1

公开(公告)日：2020-05-26

申请号：US15729483

申请日：2017-10-10

Applicant: Xilinx, Inc.

Inventor： Pradip K. Kar ,  Satyaprakash Pareek ,  Shangzhi Sun ,  Bing Tian

IPC: G06F17/50

Abstract: Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.