公开(公告)号：US10969821B2

公开(公告)日：2021-04-06

申请号：US15991179

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Ryan Kinnerk ,  Bob W. Verbruggen ,  John E. McGrath

IPC: G06F1/12 ,  G06F1/14 ,  G06F1/10

Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

公开(公告)号：US20200097038A1

公开(公告)日：2020-03-26

申请号：US15991179

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Ryan Kinnerk ,  Bob W. Verbruggen ,  John E. McGrath

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/14

Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.