公开(公告)号：US20230032302A1

公开(公告)日：2023-02-02

申请号：US17385261

申请日：2021-07-26

Applicant: Xilinx, Inc.

Inventor： Luciano Lavagno ,  Xin Jin ,  Dan Liu ,  Thomas Bollaert ,  Hem C. Neema ,  Chaosheng Shi

IPC: G06F9/52 ,  G06F30/20 ,  G06F5/06

Abstract: Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is generated indicating that the strongly connected component is deadlocked in response to each kernel of the strongly connected component asserting the signal.