公开(公告)号：US20120185812A1

公开(公告)日：2012-07-19

申请号：US13005599

申请日：2011-01-13

申请人： Yanqing Deng ,  Paul A. Hyde ,  James M. Johnson ,  Todd G. McKenzie ,  Scott K. Springer ,  Richard Q. Williams

发明人： Yanqing Deng ,  Paul A. Hyde ,  James M. Johnson ,  Todd G. McKenzie ,  Scott K. Springer ,  Richard Q. Williams

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit.

摘要翻译： 一种用于开发集成电路内的子电路的精简网表的系统和方法，以及基于精简网表而不是完整的网表来对集成电路的性能进行建模。 IC布局被分割成多个子电路，每个子电路包括通过类似的电阻网络连接到（即共享）相同的电子电路终端的给定类型的有源设备中的一个或多个的组 它们受到大致相同的总体组合寄生电阻）。 从布局中提取与子电路对应的完整网表，并进行浓缩。 每个浓缩网表列出了子电路中的有源器件和电阻网络所呈现的性能变化（例如，作为工作电源电压，工作温度以及任选的自发热和/或应力的变化的函数）。 然后在集成电路的工作温度和工作电源电压的全范围内模拟子电路的精简网表，以便为集成电路生成性能模型。

公开(公告)号：US08392867B2

公开(公告)日：2013-03-05

申请号：US13005599

申请日：2011-01-13

申请人： Yanqing Deng ,  Paul A. Hyde ,  James M. Johnson ,  Todd G. McKenzie ,  Scott K. Springer ,  Richard Q. Williams

发明人： Yanqing Deng ,  Paul A. Hyde ,  James M. Johnson ,  Todd G. McKenzie ,  Scott K. Springer ,  Richard Q. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit.

摘要翻译： 一种用于开发集成电路内的子电路的精简网表的系统和方法，以及基于精简网表而不是完整的网表来对集成电路的性能进行建模。 IC布局被分割成多个子电路，每个子电路包括通过类似的电阻网络连接到（即共享）相同的电子电路终端的给定类型的有源设备中的一个或多个的组 它们受到大致相同的总体组合寄生电阻）。 从布局中提取与子电路对应的完整网表，并进行浓缩。 每个浓缩网表列出了子电路中的有源器件和电阻网络所呈现的性能变化（例如，作为工作电源电压，工作温度以及任选的自发热和/或应力的变化的函数）。 然后在集成电路的工作温度和工作电源电压的全范围内模拟子电路的精简网表，以便为集成电路生成性能模型。

公开(公告)号：US08453101B1

公开(公告)日：2013-05-28

申请号：US13302350

申请日：2011-11-22

申请人： James M. Johnson ,  Scott K. Springer ,  Rainer Thoma ,  Josef S. Watts

发明人： James M. Johnson ,  Scott K. Springer ,  Rainer Thoma ,  Josef S. Watts

IPC分类号： G06F11/22 ,  G06F17/50

CPC分类号： G06F17/5045

摘要： Disclosed are embodiments of a method, system and program storage device for generating accurate performance targets for active semiconductor devices during technology node development in order to reduce the number of iterations required for model extraction and/or to improve model quality. In these embodiments, initial sets of performance targets for related semiconductor devices are generated, e.g., by making assumptions based on hardware measurements taken from semiconductor devices in prior technology nodes. Additional processes are then performed on the initial sets of performance targets prior to the modeling stage in order to detect and resolve any inconsistencies between the data in the sets. Specifically, plotting techniques are performed with respect to the performance targets. The results are analyzed to detect any inconsistencies indicating that the performance targets are inaccurate and adjustments are made to the performance targets in order to resolve those inconsistencies.

摘要翻译： 公开了用于在技术节点开发期间产生有源半导体器件的精确性能目标的方法，系统和程序存储装置的实施例，以便减少模型提取所需的迭代次数和/或提高模型质量。 在这些实施例中，例如通过基于从现有技术节点中的半导体器件获得的硬件测量值做出假设来生成相关半导体器件的初始的性能目标集合。 然后在建模阶段之前对初始的性能目标集进行其他过程，以便检测和解决集合中的数据之间的任何不一致。 具体地，针对性能目标执行绘图技术。 分析结果以检测指示性能目标不准确的任何不一致性，并对性能目标进行调整以解决这些不一致。

公开(公告)号：US20130132925A1

公开(公告)日：2013-05-23

申请号：US13302350

申请日：2011-11-22

申请人： James M. Johnson ,  Scott K. Springer ,  Rainer Thoma ,  Josef S. Watts

发明人： James M. Johnson ,  Scott K. Springer ,  Rainer Thoma ,  Josef S. Watts

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Disclosed are embodiments of a method, system and program storage device for generating accurate performance targets for active semiconductor devices during technology node development in order to reduce the number of iterations required for model extraction and/or to improve model quality. In these embodiments, initial sets of performance targets for related semiconductor devices are generated, e.g., by making assumptions based on hardware measurements taken from semiconductor devices in prior technology nodes. Additional processes are then performed on the initial sets of performance targets prior to the modeling stage in order to detect and resolve any inconsistencies between the data in the sets. Specifically, plotting techniques are performed with respect to the performance targets. The results are analyzed to detect any inconsistencies indicating that the performance targets are inaccurate and adjustments are made to the performance targets in order to resolve those inconsistencies.

摘要翻译： 公开了用于在技术节点开发期间产生有源半导体器件的精确性能目标的方法，系统和程序存储装置的实施例，以便减少模型提取所需的迭代次数和/或提高模型质量。 在这些实施例中，例如通过基于从现有技术节点中的半导体器件获得的硬件测量值做出假设来生成相关半导体器件的初始的性能目标集合。 然后在建模阶段之前对初始的性能目标集进行其他过程，以便检测和解决集合中的数据之间的任何不一致。 具体地，针对性能目标执行绘图技术。 分析结果以检测指示性能目标不准确的任何不一致性，并对性能目标进行调整以解决这些不一致。

公开(公告)号：US08032349B2

公开(公告)日：2011-10-04

申请号：US11626915

申请日：2007-01-25

申请人： Sim Y. Loo ,  Steven G. Lovejoy ,  Myung-Hee Na ,  Edward J. Nowak ,  Scott K. Springer

发明人： Sim Y. Loo ,  Steven G. Lovejoy ,  Myung-Hee Na ,  Edward J. Nowak ,  Scott K. Springer

IPC分类号： G06F17/50 ,  G06F7/60

CPC分类号： G06F17/5036

摘要： Disclosed herein are embodiments of an automated, fast and efficient method of generating a customized compact model that represents a semiconductor device at the chip, wafer or multi-wafer level in a specific manufacturing environment. Specifically, measurement data is collected from a specific manufacturing environment and sorted by channel lengths. Then, an optimizer is used to generate customized modeling parameters based on the measurement data. The optimization processes is a multi-step process. First, a first set of modeling parameters is generated based on measurement data associated with a long channel length. Second, a second set of modeling parameters is generated based on the first set and on measurement data associated with a short channel length. Finally, the customized modeling parameters are generated based on both the first set and the second set. The customized modeling parameters are used to generate a customized compact device model representative of the specific manufacturing environment.

摘要翻译： 本文公开的是在特定制造环境中生成表示芯片，晶片或多晶片级的半导体器件的定制紧凑型模型的自动化，快速和有效的方法的实施例。 具体来说，从特定制造环境收集测量数据，并按通道长度进行排序。 然后，优化器用于基于测量数据生成定制的建模参数。 优化过程是一个多步骤的过程。 首先，基于与长通道长度相关联的测量数据来生成第一组建模参数。 其次，基于第一组和与短信道长度相关联的测量数据生成第二组建模参数。 最后，基于第一组和第二组生成定制的建模参数。 定制的建模参数用于生成代表特定制造环境的定制紧凑型设备模型。

公开(公告)号：US20080183442A1

公开(公告)日：2008-07-31

申请号：US11626915

申请日：2007-01-25

申请人： Sim Y. Loo ,  Steven G. Lovejoy ,  Myung-Hee Na ,  Edward J. Nowak ,  Scott K. Springer

发明人： Sim Y. Loo ,  Steven G. Lovejoy ,  Myung-Hee Na ,  Edward J. Nowak ,  Scott K. Springer

IPC分类号： G06F17/10 ,  G06G7/48 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： Disclosed herein are embodiments of an automated, fast and efficient method of generating a customized compact model that represents a semiconductor device at the chip, wafer or multi-wafer level in a specific manufacturing environment. Specifically, measurement data is collected from a specific manufacturing environment and sorted by channel lengths. Then, an optimizer is used to generate customized modeling parameters based on the measurement data. The optimization processes is a multi-step process. First, a first set of modeling parameters is generated based on measurement data associated with a long channel length. Second, a second set of modeling parameters is generated based on the first set and on measurement data associated with a short channel length. Finally, the customized modeling parameters are generated based on both the first set and the second set. The customized modeling parameters are used to generate a customized compact device model representative of the specific manufacturing environment.

摘要翻译： 本文公开的是在特定制造环境中生成表示芯片，晶片或多晶片级的半导体器件的定制紧凑型模型的自动化，快速和有效的方法的实施例。 具体来说，从特定制造环境收集测量数据，并按通道长度进行排序。 然后，优化器用于基于测量数据生成定制的建模参数。 优化过程是一个多步骤的过程。 首先，基于与长通道长度相关联的测量数据来生成第一组建模参数。 其次，基于第一组和与短信道长度相关联的测量数据生成第二组建模参数。 最后，基于第一组和第二组生成定制的建模参数。 定制的建模参数用于生成代表特定制造环境的定制紧凑型设备模型。

公开(公告)号：US20080028353A1

公开(公告)日：2008-01-31

申请号：US11458240

申请日：2006-07-18

申请人： Ning Lu ,  Scott K. Springer

发明人： Ning Lu ,  Scott K. Springer

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An extraction, simulation, and analysis combined method is employed to account for the parasitic couplings from interconnect wires. Variations of parasitic resistance, capacitance, and inductance are used in circuit analysis calculators, including considering the variations of the parasitics on worst case circuit performance, skewing, and statistical Monte Carlo analysis. Each parasitic element is modeled as a call-up function with associated process distributions. Circuit analysis, such as a SPICE analysis is performed on the selected models.

摘要翻译： 采用提取，模拟和分析组合方法来考虑互连线的寄生耦合。 寄生电阻，电容和电感的变化用于电路分析计算器，包括考虑最坏情况下电路性能，偏斜和统计蒙特卡罗分析的寄生效应的变化。 每个寄生元件被建模为具有相关过程分布的调用函数。 对所选模型进行电路分析，如SPICE分析。