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5 条记录 (耗时 0.043 秒)

    Data processor
    1.
    发明授权
    Data processor 失效
    数据处理器

    公开(公告)号：US4989208A

    公开(公告)日：1991-01-29

    申请号：US39695

    申请日：1987-04-20

    申请人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    发明人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    IPC分类号： G06F11/22 ,  G06F11/267 ,  G06F15/78

    CPC分类号： G06F11/2236 ,  G06F15/7814

    摘要： In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.

    摘要翻译： 在单片机中，形成诸如中央处理单元（CPU），用于存储程序的ROM，用于存储数据的RAM和用于输入和数据输出的I / O电路等功能块 在一个半导体衬底上。 地址数据用于选择CPU必须提供地址数据的内部总线中的功能块的预定区域。 缓冲电路能够从外部设备提供地址数据，并且被提供在微计算机中。 当功能块被测试时，地址数据直接从外部测试器提供给功能块，而不用CPU的指令执行，并且必要的数据从预定功能块的区域输出，通过缓冲电路，并且是 直接读取外部设备。 因此，提高了测试效率。

    Data processor
    2.
    发明授权
    Data processor 失效
    数据处理器

    公开(公告)号：US5247521A

    公开(公告)日：1993-09-21

    申请号：US848547

    申请日：1992-03-09

    申请人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    发明人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    IPC分类号： G06F11/267 ,  G06F15/78

    CPC分类号： G06F11/2236 ,  G06F15/7814

    摘要： In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.

    摘要翻译： 在单片机中，形成诸如中央处理单元（CPU），用于存储程序的ROM，用于存储数据的RAM和用于输入和数据输出的I / O电路等功能块 在一个半导体衬底上。 地址数据用于选择CPU必须提供地址数据的内部总线中的功能块的预定区域。 缓冲电路能够从外部设备提供地址数据，并且被提供在微计算机中。 当功能块被测试时，地址数据直接从外部测试器提供给功能块，而不用CPU的指令执行，并且必要的数据从预定功能块的区域输出，通过缓冲电路，并且是 直接读取外部设备。 因此，提高了测试效率。

    Data processor
    3.
    发明授权
    Data processor 失效
    数据处理器

    公开(公告)号：US5142536A

    公开(公告)日：1992-08-25

    申请号：US584608

    申请日：1990-09-19

    申请人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    发明人： Yasushi Akao ,  Shinkichi Hotta ,  Haruo Keida

    IPC分类号： G06F11/22 ,  G06F11/267 ,  G06F15/78

    CPC分类号： G06F11/2236 ,  G06F15/7814

    摘要： In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.

    Key input circuit
    4.
    发明授权
    Key input circuit 失效
    主输入电路

    公开(公告)号：US4074262A

    公开(公告)日：1978-02-14

    申请号：US652661

    申请日：1976-01-27

    申请人： Kosei Nomiya ,  Shinkichi Hotta

    发明人： Kosei Nomiya ,  Shinkichi Hotta

    IPC分类号： G06F3/023 ,  H03M11/20 ,  G06F3/02

    CPC分类号： H03M11/20

    摘要： A key input circuit includes a binary-coded N-ary counter consisting of a plurality of binary counters, a decoder decoding coded pulse outputs of the counter for converting the counter outputs into a plurality of timing pulse signals, which are applied respectively to a plurality of keys. These timing pulse signals form a key information input by manipulation of the corresponding key, and a plurality of gates are provided for coding the key information by gating the input provided by the specific coded pulse output of the counter in response to receipt of the control input provided by the specific key signal applied through the manipulated key.