摘要:
Methods and apparatus for optimizing idle mode stand-by time in wireless device operable in a multicast system are disclosed. In order to maximize or optimize the stand-by time for idle mode, a time line for decoding of overhead information symbol (OIS) data received in one or more superframes in the wireless device. Based on the determined time line, an offset time period can be determined for setting an idle mode timer period used by the wireless device to decode the OIS information. By offsetting the timer period, a wireless device can be ensured to wake up and prepared to latch OIS information before the start of a superframe boundary, thus minimizing the wake up time of the device operating in an idle mode and, in turn, optimizing stand-by time.
摘要:
Methods and apparatus for optimizing idle mode stand-by time in wireless device operable in a multicast system are disclosed. In order to maximize or optimize the stand-by time for idle mode, a time line for decoding of overhead information symbol (OIS) data received in one or more superframes in the wireless device. Based on the determined time line, an offset time period can be determined for setting an idle mode timer period used by the wireless device to decode the OIS information. By offsetting the timer period, a wireless device can be ensured to wake up and prepared to latch OIS information before the start of a superframe boundary, thus minimizing the wake up time of the device operating in an idle mode and, in turn, optimizing stand-by time.
摘要:
Embodiments of the present invention relate to machines that perform in-system programming of programmable devices that are attached to assembled printed circuit boards. In accordance with one aspect, multiple nonvolatile devices may be programmed in a single session at their normal maximum programming speeds. Different nonvolatile devices on a board can receive different data. Data variables can be inserted so that not all boards receive identical data. A master controller sends image files and algorithm information to a subsidiary controller. The subsidiary controller executes a device algorithm, and an FPGA executes a bus algorithm. Embodiments of the present invention can be designed as stand-alone systems or to operate cooperatively with an automatic tester, so that testing and device programming can take place in a single operation using a single fixture to hold the circuit board.