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    Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit
    1.
    发明授权
    Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit 失效
    具有测试地址产生电路的半导体存储器件和具有测试地址产生电路的半导体存储器件的测试方法

    公开(公告)号：US08051341B2

    公开(公告)日：2011-11-01

    申请号：US12214453

    申请日：2008-06-19

    申请人： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-II Kim

    发明人： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-II Kim

    IPC分类号： G11C29/00

    CPC分类号： G11C29/20 ,  G11C2029/3602

    摘要： A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

    摘要翻译： 半导体存储器件包括在该器件上配置的测试地址产生电路。 测试地址产生电路响应于至少一个外部施加的测试地址产生信号，产生用于半导体存储器件测试的多个测试地址。 结果，基于所需地址引脚的减少，DUT的数量可以增加，并且半导体存储器件的制造生产率和测试效率可以增加。