公开(公告)号：US08458633B2

公开(公告)日：2013-06-04

申请号：US13262759

申请日：2010-04-21

申请人： Yoshihiro Ono ,  Takeshi Watanabe ,  Naoshi Doi ,  Itsuki Yamada ,  Tsuneo Tsukagoshi

发明人： Yoshihiro Ono ,  Takeshi Watanabe ,  Naoshi Doi ,  Itsuki Yamada ,  Tsuneo Tsukagoshi

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06G7/62

CPC分类号： G06F17/5031

摘要： A semiconductor integrated circuit design apparatus for analyzing a delay in a semiconductor integrated circuit. The semiconductor integrated circuit includes a delay analysis unit, a noise generation unit, a voltage fluctuation level analysis unit and a timing verification unit. The noise generation unit generates noise information based on a predetermined noise definition and the voltage fluctuation level analysis unit analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the generated noise information. Further, the timing verification unit makes the delay analysis unit analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis.

摘要翻译： 一种用于分析半导体集成电路中的延迟的半导体集成电路设计装置。 半导体集成电路包括延迟分析单元，噪声生成单元，电压波动水平分析单元和定时验证单元。 噪声发生单元基于预定的噪声清晰度生成噪声信息，并且电压波动水平分析单元基于所生成的噪声信息来分析当施加噪声时半导体集成电路的电压波动水平。 此外，定时验证单元使得延迟分析单元基于分析的电压波动水平来分析静态延迟，以基于静态延迟分析的结果来验证半导体集成电路的操作的定时。

公开(公告)号：US08341579B2

公开(公告)日：2012-12-25

申请号：US13062263

申请日：2009-10-27

申请人： Takumi Okamoto ,  Takeshi Watanabe ,  Itsuki Yamada ,  Naoshi Doi ,  Tsuneo Tsukagoshi

发明人： Takumi Okamoto ,  Takeshi Watanabe ,  Itsuki Yamada ,  Naoshi Doi ,  Tsuneo Tsukagoshi

IPC分类号： G06F17/50

CPC分类号： G01R31/2848 ,  G06F17/5036

摘要： An operation analyzing apparatus (100) for semiconductor integrated circuits according to this exemplary embodiment includes a simulation analyzing unit (140), and the simulation analyzing unit (140) includes: a semiconductor characteristics extracting unit (110) that extracts the inductances L, resistances R, and capacitances C of a board, a package, and a semiconductor integrated circuit, from the semiconductor integrated circuit mounted on the board via the package; an individual network generating unit (111) that generates individual networks of the extracted inductance L, resistance R, and capacitance C with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; an integrated network generating unit (112) that generates an integrated network by integrating all of the generated individual networks; and an operation simulation running unit (113) that performs an operation simulation of the semiconductor integrated circuit by inserting a test noise pattern to an arbitrary position in the generated integrated network.

摘要翻译： 根据本实施方式的半导体集成电路的动作分析装置（100）具有模拟分析部（140），所述模拟分析部（140）具备：提取电感L，电阻 R和电容C，从安装在板上的半导体集成电路经由封装形成的板，封装和半导体集成电路; 单个网络生成单元（111），其针对所述半导体衬底，所述封装和所述半导体集成电路中的每一个产生提取的电感L，电阻R和电容C的各个网络; 集成网络生成单元（112），其通过集成所有生成的各个网络来生成集成网络; 以及通过将测试噪声模式插入到所生成的集成网络中的任意位置来执行半导体集成电路的操作模拟的操作模拟运行单元（113）。

公开(公告)号：US20110296369A1

公开(公告)日：2011-12-01

申请号：US13062263

申请日：2009-10-27

申请人： Takumi Okamoto ,  Takeshi Watanabe ,  Itsuki Yamada ,  Naoshi Doi ,  Tsuneo Tsukagoshi

发明人： Takumi Okamoto ,  Takeshi Watanabe ,  Itsuki Yamada ,  Naoshi Doi ,  Tsuneo Tsukagoshi

IPC分类号： G06F11/22

CPC分类号： G01R31/2848 ,  G06F17/5036

摘要： An operation analyzing apparatus (100) for semiconductor integrated circuits according to this exemplary embodiment includes a simulation analyzing unit (140), and the simulation analyzing unit (140) includes: a semiconductor characteristics extracting unit (110) that extracts the inductances L, resistances R, and capacitances C of a board, a package, and a semiconductor integrated circuit, from the semiconductor integrated circuit mounted on the board via the package; an individual network generating unit (111) that generates individual networks of the extracted inductance L, resistance R, and capacitance C with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; an integrated network generating unit (112) that generates an integrated network by integrating all of the generated individual networks; and an operation simulation running unit (113) that performs an operation simulation of the semiconductor integrated circuit by inserting a test noise pattern to an arbitrary position in the generated integrated network.

摘要翻译： 根据本实施方式的半导体集成电路的动作分析装置（100）具有模拟分析部（140），所述模拟分析部（140）具备：提取电感L，电阻 R和电容C，从安装在板上的半导体集成电路经由封装形成的板，封装和半导体集成电路; 单个网络生成单元（111），其针对所述半导体衬底，所述封装和所述半导体集成电路中的每一个产生提取的电感L，电阻R和电容C的各个网络; 集成网络生成单元（112），其通过集成所有生成的各个网络来生成集成网络; 以及通过将测试噪声模式插入到所生成的集成网络中的任意位置来执行半导体集成电路的操作模拟的操作模拟运行单元（113）。

公开(公告)号：US20120096421A1

公开(公告)日：2012-04-19

申请号：US13262759

申请日：2010-04-21

申请人： Yoshihiro Ono ,  Takeshi Watanabe ,  Naoshi Doi ,  Itsuki Yamada ,  Tsuneo Tsukagoki

发明人： Yoshihiro Ono ,  Takeshi Watanabe ,  Naoshi Doi ,  Itsuki Yamada ,  Tsuneo Tsukagoki

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A semiconductor integrated circuit design apparatus (100) includes a delay analysis unit (102) which analyzes a static delay in respective paths of a semiconductor integrated circuit, a noise generation unit (104) which generates noise information based on a predetermined noise definition, a voltage fluctuation level analysis unit (106) which analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the noise information, and a timing verification unit (108) which makes the delay analysis unit (102) analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis, wherein the noise generation unit (104) generates noise information on noise applied at predetermined application timing, and the timing verification unit (108) verifies the timing for each noise applied with the predetermined application timing.

摘要翻译： 半导体集成电路设计装置（100）包括分析半导体集成电路的各个路径中的静态延迟的延迟分析单元（102），基于预定噪声定义产生噪声信息的噪声生成单元（104） 电压波动电平分析单元（106），其基于噪声信息分析施加了噪声时的半导体集成电路的电压波动水平;以及定时验证单元（108），其使得所述延迟分析单元（102）分析静态 基于所分析的电压波动水平的延迟，基于静态延迟分析的结果来验证半导体集成电路的操作的定时，其中，噪声产生单元（104）产生关于在预定应用定时处施加的噪声的噪声信息，并且 定时验证单元（108）根据预定的应用定时验证每个噪声的定时。