公开(公告)号：US5185283A

公开(公告)日：1993-02-09

申请号：US666452

申请日：1991-03-04

申请人： Yuko Fukui ,  Katsuhiro Ohtani ,  Hiroyuki Miyamoto ,  Masao Nishiura ,  Moriyuki Chimura

发明人： Yuko Fukui ,  Katsuhiro Ohtani ,  Hiroyuki Miyamoto ,  Masao Nishiura ,  Moriyuki Chimura

IPC分类号： H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L2924/0002

摘要： This invention is to realize a final circuit by wiring only the top layer depending on the individual circuits, by fabricating a master slice in the step of up to forming plural semiconductor elements such as transistors on a semiconductor substrate, forming a lower layer of versatile wiring pieces thereon, and forming contact holes thereon. In this way, since the step just before formation of the top layer wiring can be carried out regardless of the features of individual circuits, preliminary mass productions are possible, and final products can be completed only by forming the wiring of the top layer depending on the requirements of the users. Accordingly, it is applicable to a wide variety of products, and the term for development and manufacture can be tremendously shortened.

摘要翻译： 本发明是通过在半导体衬底上形成诸如晶体管之类的多个半导体元件的步骤中制造母片来形成根据各个电路的顶层来实现最终电路，形成多层布线 并在其上形成接触孔。 以这种方式，由于可以在形成顶层布线之前的步骤进行，而不管各个电路的特征如何，所以可以进行初步的批量生产，并且可以仅通过形成顶层的布线来完成最终产品 用户的要求。 因此，适用于各种产品，开发制造的术语可以大大缩短。