Efficient parallel floating point exception handling in a processor
    1.
    发明申请
    Efficient parallel floating point exception handling in a processor 有权
    处理器中的高效并行浮点异常处理

    公开(公告)号:US20090327665A1

    公开(公告)日:2009-12-31

    申请号:US12217084

    申请日:2008-06-30

    IPC分类号: G06F9/302

    摘要: Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.

    摘要翻译: 公开了用于处理执行单指令多数据(SIMD)指令的处理器中的浮点异常的方法和装置。 在一个实施例中,识别用于SIMD浮点运算的数字异常,并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。 启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化,以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。 标志被设置和存储与打包部分结果以识别异常元素。 在一个实施例中,当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

    Efficient parallel floating point exception handling in a processor
    2.
    发明授权
    Efficient parallel floating point exception handling in a processor 有权
    处理器中的高效并行浮点异常处理

    公开(公告)号:US09092226B2

    公开(公告)日:2015-07-28

    申请号:US13325559

    申请日:2011-12-14

    IPC分类号: G06F9/38 G06F9/30

    摘要: Methods and apparatus are provided for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one example a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one example a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.

    摘要翻译: 提供了用于处理执行单指令多数据(SIMD)指令的处理器中的浮点异常的方法和装置。 在一个示例中,识别用于SIMD浮点运算的数字异常,并且启动SIMD微操作以生成用于SIMD浮点运算的打包结果的两个打包部分结果。 启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化,以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。 标志被设置和存储与打包部分结果以识别异常元素。 在一个示例中,当SIMD归一化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

    Efficient parallel floating point exception handling in a processor
    3.
    发明授权
    Efficient parallel floating point exception handling in a processor 有权
    处理器中的高效并行浮点异常处理

    公开(公告)号:US08103858B2

    公开(公告)日:2012-01-24

    申请号:US12217084

    申请日:2008-06-30

    IPC分类号: G06F9/00

    摘要: Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.

    摘要翻译: 公开了用于处理执行单指令多数据(SIMD)指令的处理器中的浮点异常的方法和装置。 在一个实施例中,识别用于SIMD浮点运算的数字异常,并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。 启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化,以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。 标志被设置和存储与打包部分结果以识别异常元素。 在一个实施例中,当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

    Efficient Parallel Floating Point Exception Handling In A Processor
    4.
    发明申请
    Efficient Parallel Floating Point Exception Handling In A Processor 审中-公开
    处理器中有效的并行浮点异常处理

    公开(公告)号:US20120084533A1

    公开(公告)日:2012-04-05

    申请号:US13325559

    申请日:2011-12-14

    IPC分类号: G06F9/30 G06F9/38 G06F9/302

    摘要: Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.

    摘要翻译: 公开了用于处理执行单指令多数据(SIMD)指令的处理器中的浮点异常的方法和装置。 在一个实施例中,识别用于SIMD浮点运算的数字异常,并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。 启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化,以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。 标志被设置和存储与打包部分结果以识别异常元素。 在一个实施例中,当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。