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公开(公告)号：US08117039B2
公开(公告)日：2012-02-14
申请号：US12334779
申请日：2008-12-15
IPC分类号： G10L19/00
CPC分类号： G10L19/173 , H03H17/0294 , H03H17/0685
摘要： A multi-stage recursive sample rate converter (“SRC”) typically embodied as digital signal processor provides for an efficient structure for converting digital audio samples at one frequency, such as 48 kHz, to another frequency, such as 44.1 kHz. A parameter codebook comprising memory stores parameters used at a plurality of stages by the SRC. For each stage, a controller coordinates the SRC to use the appropriate set of parameters from the codebook, process an input audio sample stream, and store the intermediate results in a buffer. The controller then causes the intermediate results to be processed again as input to the SRC in a subsequent stage of processing using a different set of parameters. The process is repeated until all stages are completed, and the final results are the output digital audio data stream at the desired sampling rate.
摘要翻译： 通常实现为数字信号处理器的多级递归采样率转换器（“SRC”）提供了将一个频率（例如48 kHz）的数字音频采样转换为另一个频率（如44.1 kHz）的有效结构。 包括存储器的参数码本存储由SRC在多个级中使用的参数。 对于每个阶段，控制器协调SRC以使用来自码本的适当的参数集，处理输入音频样本流，并将中间结果存储在缓冲器中。 然后，控制器使得使用不同的参数集在后续处理阶段中再次处理中间结果作为SRC的输入。 重复该过程直到所有阶段完成，并且最终结果是以期望的采样速率输出的数字音频数据流。
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公开(公告)号：US20100153122A1
公开(公告)日：2010-06-17
申请号：US12334779
申请日：2008-12-15
IPC分类号： G10L19/00
CPC分类号： G10L19/173 , H03H17/0294 , H03H17/0685
摘要： A multi-stage recursive sample rate converter (“SRC”) typically embodied as digital signal processor provides for an efficient structure for converting digital audio samples at one frequency, such as 48 kHz, to another frequency, such as 44.1 kHz. A parameter codebook comprising memory stores parameters used at a plurality of stages by the SRC. For each stage, a controller coordinates the SRC to use the appropriate set of parameters from the codebook, process an input audio sample stream, and store the intermediate results in a buffer. The controller then causes the intermediate results to be processed again as input to the SRC in a subsequent stage of processing using a different set of parameters. The process is repeated until all stages are completed, and the final results are the output digital audio data stream at the desired sampling rate.
摘要翻译： 通常实现为数字信号处理器的多级递归采样率转换器（“SRC”）提供了将一个频率（例如48 kHz）的数字音频采样转换为另一个频率（如44.1 kHz）的有效结构。 包括存储器的参数码本存储由SRC在多个级中使用的参数。 对于每个阶段，控制器协调SRC以使用来自码本的适当的参数集，处理输入音频样本流，并将中间结果存储在缓冲器中。 然后，控制器使得使用不同的参数集在后续处理阶段中再次处理中间结果作为SRC的输入。 重复该过程直到所有阶段完成，并且最终结果是以期望的采样速率输出的数字音频数据流。
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