公开(公告)号：US20250168971A1

公开(公告)日：2025-05-22

申请号：US18513419

申请日：2023-11-17

Applicant: Ampere Computing LLC

Inventor： Sammy HINDI ,  Chandan BHAT ,  Christopher WYLAND ,  Surya KONERU ,  Shengjun QIN ,  Mu-chen TSAI ,  Kirk LOWRY ,  Lei SHAN ,  Mysore DIVAKAR ,  Quang D. LE ,  Xiaotong HE ,  Yoham Niranjan PARELKAR ,  Alex M. GREGORY ,  Yuyin YU

IPC: H05K1/02 ,  G06F13/38

Abstract: Techniques for trace width modulation are disclosed. In an aspect, a method for trace width modulation may include determining that a region along a length of a trace has an impedance that is different from a target impedance for the trace, and altering a width of at least a portion of the trace within the region to cause the impedance of the trace to be substantially equal to the target impedance of the trace.

公开(公告)号：US20250130852A1

公开(公告)日：2025-04-24

申请号：US18490660

申请日：2023-10-19

Applicant: Ampere Computing LLC

Inventor： Benjamin Crawford CHAFFIN ,  Raymond Scott TETRICK

IPC: G06F9/48

Abstract: Disclosed are techniques for a request node device that is communicatively coupled to one or more completer devices via a mesh network. In an aspect, the request node device may receive multiple completer workload indicators, one after another, each one of the completer workload indicators indicating a level of activity of a corresponding completer device of the one or more completer devices. The request node devices may, for each one of the completer workload indicators received by the request node device, determine a current mapped workload value of a current completer workload indicator, update a current accumulation value based on the current mapped workload value and a previous accumulation value, and update a workload setting of the request node device for the workload throttling based on the current accumulation value.

公开(公告)号：US20250130804A1

公开(公告)日：2025-04-24

申请号：US18490690

申请日：2023-10-19

Applicant: Ampere Computing LLC

Inventor： Jonathan Christopher PERRY ,  David Paul TURLEY ,  Benjamin Crawford CHAFFIN

IPC: G06F9/30

Abstract: Disclosed are techniques for optimizing store of common values to memory structures. In an aspect, a method for instruction decoding may include obtaining a store instruction that involves two or more registers. The method may include determining that at least one register of the two or more registers comprises an all-zeros value. The method may also include decoding the store instruction into a store-zeros micro-operation based at least in part on the determining. In some examples of the method, zeros-indicating metadata may be used to indicate that an all-zeros value has been stored in a memory structure.

公开(公告)号：US20250130729A1

公开(公告)日：2025-04-24

申请号：US18490673

申请日：2023-10-19

Applicant: Ampere Computing LLC

Inventor： Raymond Scott TETRICK ,  Nagi ABOULENEIN ,  Massimo SUTERA ,  Shivnandan KAUSHIK

IPC: G06F3/06

Abstract: Disclosed are techniques for memory resource control using Memory System Resource Partitioning and Monitoring (MPAM). In an aspect, a method of memory-system resource usage monitoring on a processing unit may include attaching a partition identifier from a set of partition identifiers to each memory access request of a plurality of memory access requests on an interconnect. The method may also include interleaving each memory access request of the plurality of memory access requests to a set of memory system components. The method may also include determining a first bandwidth associated with a first memory system component of the set of memory system components. The method may also include applying the first bandwidth associated with the first memory system component to one or more other memory system components of the set of memory system components based at least in part on the interleaving each memory access request.

公开(公告)号：US20250110902A1

公开(公告)日：2025-04-03

申请号：US18478645

申请日：2023-09-29

Applicant: Ampere Computing LLC

Inventor： Benjamin Crawford Chaffin ,  Shivnandan Kaushik ,  Matthew Robert Erler

IPC: G06F13/28

Abstract: A processor that includes a memory tagging extension (MTE) provides default tag bits employed when external devices, which are not compliant with MTE, access the memory circuit (e.g., employing direct memory access (DMA)). The default tag bits are stored as first tag bits with the data in memory. The processing circuit can include a mode indicator indicating whether default tag bits are employed. In a first mode, in which the default tag bits are not employed, an exception signal may be immediately generated in response to a mismatch between the first tag bits and second tag bits in the memory instruction. In a second mode, in response to a mismatch, the first tag bits are 10 further compared to the default tag bits and an error may be generated in response to a mismatch between the first tag bits and the default tag bits.

公开(公告)号：US12228994B2

公开(公告)日：2025-02-18

申请号：US17472319

申请日：2021-09-10

Applicant: Ampere Computing LLC

Inventor： Sarthak Raina ,  Sanjay Patel ,  Hoan Tran ,  Mitrajit Chatterjee ,  Abhishek Niraj ,  Anuradha Raghunathan

IPC: G06F1/324 ,  G01R21/133 ,  G06F1/3206 ,  G06F1/3296

Abstract: A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

公开(公告)号：US12175243B2

公开(公告)日：2024-12-24

申请号：US16722870

申请日：2019-12-20

Applicant: Ampere Computing LLC

Inventor： Jonathan Christopher Perry ,  Jason Anthony Bessette ,  Sean Philip Mirkes ,  Jacob Daniel Morgan ,  John Saint Tran

IPC: G06F9/30 ,  G06F9/38

Abstract: Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.

公开(公告)号：US12159056B2

公开(公告)日：2024-12-03

申请号：US17856299

申请日：2022-07-01

Applicant: Ampere Computing LLC

Inventor： Massimo Sutera ,  Sandeep Brahmadathan ,  Nagi Aboulenein ,  Brian Thomas Chase ,  James Edward Casteel ,  Kha Minh Huynh ,  Vung Thanh Huynh

IPC: G06F3/06

Abstract: Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.

公开(公告)号：US12141587B2

公开(公告)日：2024-11-12

申请号：US17808946

申请日：2022-06-24

Applicant: Ampere Computing LLC

Inventor： Kha Hong Nguyen ,  Harb Ali Abdulhamid

IPC: G06F9/4401

Abstract: Generalized boot operations for disaggregated, multiple (multi-) semiconductor die (“die”) computing system, and related methods and computer-readable media are disclosed. In exemplary aspects, to provide for generalized boot-up firmware/software for the computing system that does not have to be reconfigured for different configurations of dies in variations of IC packages, a CPU die (or other die) designated as a primary die is configured to perform a discoverable boot process over a side-band discovery bus to discover the other dies present in an IC package of the computing system and to then control their boot-up operations. In this manner, the boot-up firmware/software executed by the primary die to boot-up the computing system can be generalized irrespective of the number of dies and their particular configuration. In this manner, a generalized boot-up firmware/software can be provided to control boot-up operations of the computing system independent of specific dies included.

公开(公告)号：US11966750B2

公开(公告)日：2024-04-23

申请号：US17809891

申请日：2022-06-29

Applicant: Ampere Computing LLC

Inventor： Shivnandan Kaushik ,  Harb Abdulhamid ,  Vanshidhar Konda ,  Yogesh Bansal ,  Sachhidh Kannan ,  Sebastien Hily

IPC: G06F9/4401 ,  G06F9/48 ,  G06F15/173

CPC classification number: G06F9/4403 ,  G06F9/4812 ,  G06F15/17381

Abstract: Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.