公开(公告)号：US09275185B2

公开(公告)日：2016-03-01

申请号：US14161895

申请日：2014-01-23

申请人： R3 Logic, Inc.

发明人： Lisa G. McIlrath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045 ,  G06F17/5068

摘要： Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

公开(公告)号：US08209649B2

公开(公告)日：2012-06-26

申请号：US12537500

申请日：2009-08-07

申请人： Lisa G. McIlrath

发明人： Lisa G. McIlrath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045 ,  G06F17/5068

摘要： Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

摘要翻译： 公开了用于垂直集成的三维集成电路的计算机辅助设计工具生成和验证电路布局的方法和系统。 在一个实例中，通过提供两个或多个电路电平的标识符来获得这些教导的3-D技术文件，为两个或多个电路级别中的每一个提供与每个电路级别对应的2-D技术文件的标识符 所述一个或多个电路电平并且提供包括对应于所述一个或多个电路电平中的每个电路电平的两个或更多个电路电平的文件结构和与所述两个或更多个电路中的每一个对应的2-D技术文件的文件结构 电路电平。 公开了其他实施例。

公开(公告)号：US20140137061A1

公开(公告)日：2014-05-15

申请号：US14161895

申请日：2014-01-23

申请人： R3 Logic, Inc.

发明人： Lisa G. McIlrath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045 ,  G06F17/5068

摘要： Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

摘要翻译： 公开了用于垂直集成的三维集成电路的计算机辅助设计工具生成和验证电路布局的方法和系统。 在一个实例中，通过提供两个或多个电路电平的标识符来获得这些教导的3-D技术文件，为两个或多个电路级别中的每一个提供与每个电路级别对应的2-D技术文件的标识符 所述一个或多个电路电平并且提供包括对应于所述一个或多个电路电平中的每个电路电平的两个或更多个电路电平的文件结构和与所述两个或更多个电路中的每一个对应的2-D技术文件的文件结构 电路电平。 公开了其他实施例。

公开(公告)号：US08464191B2

公开(公告)日：2013-06-11

申请号：US13187912

申请日：2011-07-21

申请人： Lisa G. McIlrath

发明人： Lisa G. McIlrath

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081

摘要： A system and method for identifying circuit components of an integrated circuit includes a processor identifying geometric characteristics of an integrated circuit and sorting the geometric characteristics by order of occurrence of each geometric characteristic. Co-occurring arrangements of the geometric characteristics are then identified and used to identify a standard cell. The geometric characteristics of the standard cell may then be compared to the geometric characteristics of a known cell. Each electrically significant geometric characteristic of the standard cell can be compared to the electrically significant geometric characteristics of the known cell. If the standard cell matches the known cell an instance of the standard cell can be placed in a layout. Once placing the standard cell in the layout a netlist can be extracted.

摘要翻译： 用于识别集成电路的电路部件的系统和方法包括识别集成电路的几何特性的处理器，并且通过每个几何特征的出现顺序对几何特性进行排序。 然后识别几何特征的共同排列并用于识别标准单元。 然后将标准单元的几何特征与已知单元的几何特性进行比较。 可以将标准单元的每个电显示几何特征与已知单元的电显着几何特性进行比较。 如果标准单元格与已知单元格匹配，则标准单元格的实例可以放置在布局中。 一旦将标准单元格放置在布局中，就可以提取网表。

公开(公告)号：US08266560B2

公开(公告)日：2012-09-11

申请号：US13218581

申请日：2011-08-26

申请人： Lisa G. McIlrath

发明人： Lisa G. McIlrath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045 ,  G06F17/5068

摘要： Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

公开(公告)号：US20110314437A1

公开(公告)日：2011-12-22

申请号：US13218581

申请日：2011-08-26

申请人： Lisa G. McIlrath

发明人： Lisa G. McIlrath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045 ,  G06F17/5068

摘要： Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

摘要翻译： 公开了用于垂直集成的三维集成电路的计算机辅助设计工具生成和验证电路布局的方法和系统。 在一个实例中，通过提供两个或多个电路电平的标识符来获得这些教导的3-D技术文件，为两个或多个电路级别中的每一个提供与每个电路级别对应的2-D技术文件的标识符 所述一个或多个电路电平并且提供包括对应于所述一个或多个电路电平中的每个电路电平的两个或更多个电路电平的文件结构和与所述两个或更多个电路中的每一个对应的2-D技术文件的文件结构 电路电平。 公开了其他实施例。

公开(公告)号：US20120317528A1

公开(公告)日：2012-12-13

申请号：US13585412

申请日：2012-08-14

申请人： Lisa G. McIlrath

发明人： Lisa G. McIlrath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045 ,  G06F17/5068

摘要： Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

摘要翻译： 公开了用于垂直集成的三维集成电路的计算机辅助设计工具生成和验证电路布局的方法和系统。 在一个实例中，通过提供两个或多个电路电平的标识符来获得这些教导的3-D技术文件，为两个或多个电路级别中的每一个提供与每个电路级别对应的2-D技术文件的标识符 所述一个或多个电路电平并且提供包括对应于所述一个或多个电路电平中的每个电路电平的两个或更多个电路电平的文件结构以及与所述两个或更多个电路中的每一个对应的2-D技术文件 电路电平。 公开了其他实施例。

公开(公告)号：US08032857B2

公开(公告)日：2011-10-04

申请号：US12233260

申请日：2008-09-18

申请人： Lisa G. McIlrath

发明人： Lisa G. McIlrath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045 ,  G06F17/5068

摘要： Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

摘要翻译： 公开了用于垂直集成的三维集成电路的计算机辅助设计工具生成和验证电路布局的方法和系统。 在一个实例中，通过提供两个或多个电路电平的标识符来获得这些教导的3-D技术文件，为两个或多个电路级别中的每一个提供与每个电路级别对应的2-D技术文件的标识符 所述一个或多个电路电平并且提供包括对应于所述一个或多个电路电平中的每个电路电平的两个或更多个电路电平的文件结构和与所述两个或更多个电路中的每一个对应的2-D技术文件的文件结构 电路电平。 公开了其他实施例。

公开(公告)号：US07526739B2

公开(公告)日：2009-04-28

申请号：US11485883

申请日：2006-07-13

申请人： Lisa G. McIlrath

发明人： Lisa G. McIlrath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5045 ,  G06F17/5068

摘要： Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

摘要翻译： 公开了用于垂直集成的三维集成电路的计算机辅助设计工具生成和验证电路布局的方法和系统。 在一个实例中，通过提供两个或多个电路电平的标识符来获得这些教导的3-D技术文件，为两个或多个电路级别中的每一个提供与每个电路级别对应的2-D技术文件的标识符 所述一个或多个电路电平并且提供包括对应于所述一个或多个电路电平中的每个电路电平的两个或更多个电路电平的文件结构和与所述两个或更多个电路中的每一个对应的2-D技术文件的文件结构 电路电平。 公开了其他实施例。