摘要:
A method and system for simulating in software a digital computer system by performing virtual to physical translations of simulated instructions is disclosed. The number of virtual to physical translations using hash lookups is reduced by analyzing sequences of the instructions for determining with high probability whether the memory accesses made by the instructions perform the same virtual to physical translation in order to reduce the number of necessary hash lookups to enable faster simulation performance.
摘要:
The invention relates to a computer program interpreter and a method for the same, using statistics to group (SR89, SR17 . . . SR6; SR4, SR34 . . . SR16) frequently used service routines (SR) in the same program function and to control encoding of instructions. Frequently used service routines are assigned shorter codes thus enhancing the performance of a simulator or emulator.
摘要翻译:本发明涉及一种计算机程序解释器及其方法,使用统计学来分组(SR 89,SR 17 ... SR 6; SR 4,SR 34 ... SR 16)频繁使用的服务程序(SR) 相同的程序功能和控制指令的编码。 经常使用的服务程序被分配较短的代码,从而增强了模拟器或仿真器的性能。
摘要:
The invention relates to a computer program interpreter and a method for the same, using statistics to group (SR89, SR17 . . . SR6; SR4, SR34 . . . SR16) frequently used service routines (SR) in the same program function and to control encoding of instructions. Frequently used service routines are assigned shorter codes thus enhancing the performance of a simulator or emulator.
摘要翻译:本发明涉及一种计算机程序解释器及其方法,使用统计学来分组(SR 89,SR 17 ... SR 6; SR 4,SR 34 ... SR 16)频繁使用的服务程序(SR) 相同的程序功能和控制指令的编码。 经常使用的服务程序被分配较短的代码,从而增强了模拟器或仿真器的性能。
摘要:
The present invention discloses method and system for a multimode simulator having an emulation core with improved performance. In an embodiment of the invention, the overhead caused by the exclusive use of the simulation technique using one instruction-at-a-time interpretation is reduced by additionally using binary translation for executed blocks of interpreted instructions (i.e. that contain no jumps out of the block) from the same instruction set architecture description. Since performing translations too frequently can undesirably increase overhead by overloading the cache, the binary translation is only performed for blocks that are executed frequently. Once the blocks are translated e.g. by forming the block from instructions via templates and generating the collective code, the overall simulator performance is significantly improved by running the blocks instead of running the instructions one-at-a-time.
摘要:
The invention relates to a computer program interpreter and a method for the same, using statistics to group (SR89, SR17 . . . SR6; SR4, SR34 . . . SR16) frequently used service routines (SR) in the same program function and to control encoding of instructions. Frequently used service routines are assigned shorter codes thus enhancing the performance of a simulator or emulator.
摘要:
The invention is a technique that allows very efficient execution of an instruction set simulator (ISS) when certain code fragments are simulated. They occur frequently in operating systems, when a processor waits for something to occur. These loops perform very little, if any, computation. An automatic analysis of the code fragments is performed to determine whether they can be transformed to “fast forward” when execution loops through the code fragment. This is done by the creation of a function g, that takes a number of state changes as an input and can compute the state at a time T by a single application of the function, rather than applying the next state function repeatedly until time T is reached. An important aspect of the resulting optimization is that it produces exactly the same simulated result as compared to when it is not applied, i.e. the optimization is non-intrusive.