Parallel processor that routes messages around blocked or faulty nodes
by selecting an output port to a subsequent node from a port vector and
transmitting a route ready signal back to a previous node
    1.
    发明授权
    Parallel processor that routes messages around blocked or faulty nodes by selecting an output port to a subsequent node from a port vector and transmitting a route ready signal back to a previous node 失效
    并行处理器通过从端口向量中选择到后续节点的输出端口并将路由就绪信号发送回上一个节点来将消息路由在阻塞或故障节点周围

    公开(公告)号:US5638516A

    公开(公告)日:1997-06-10

    申请号:US283572

    申请日:1994-08-01

    CPC分类号: G06F15/17381

    摘要: A parallel processor network comprised of a plurality of nodes, each node including a processor containing a number of I/O ports, and a local memory. A communication path is established through a node by comparing a target node address in a first address packet with a processor ID of the node. If node address is equal to the target node address a receive channel is allocated to the input port and a route ready command is sent over an output port paired with the input port. If the node address is not equal to the target node address, then a first unallocated output port is selected from a port vector and the address packet is forwarded to a next node over the selected output port.

    摘要翻译: 由多个节点组成的并行处理器网络,每个节点包括包含多个I / O端口的处理器和本地存储器。 通过将第一地址分组中的目标节点地址与节点的处理器ID进行比较,通过节点建立通信路径。 如果节点地址等于目标节点地址,则接收信道被分配给输入端口,并且路由就绪命令通过与输入端口配对的输出端口发送。 如果节点地址不等于目标节点地址,则从端口向量中选择第一个未分配的输出端口,并将地址数据包转发到所选输出端口上的下一个节点。

    Hypercube processor network in which the processor indentification
numbers of two processors connected to each other through port number
n, vary only in the nth bit
    2.
    发明授权
    Hypercube processor network in which the processor indentification numbers of two processors connected to each other through port number n, vary only in the nth bit 失效
    通过端口号n彼此连接的两个处理器的处理器标识号的Hypercube处理器网络仅在第n位

    公开(公告)号:US5367636A

    公开(公告)日:1994-11-22

    申请号:US144544

    申请日:1993-11-01

    CPC分类号: G06F15/17343

    摘要: A parallel processor network comprised of a plurality of nodes, each node including a processor containing a number of I/O ports, and a local memory. Each processor in the network is assigned a unique processor ID (202) such that the processor IDs of two processors connected to each other through port number n, vary only in the nth bit. Input message decoding means (200) and compare logic and message routing logic (204) create a message path through the processor in response to the decoding of an address message packet and remove the message path in response to the decoding of an end of transmission (EOT) Packet. Each address message packet includes a Forward bit used to send a message to a remote destination either within the network or to a foreign network. Each address packet includes Node Address bits that contain the processor ID of the destination node, it the destination node is in the local network. If the destination node is in a foreign network space, the destination node must be directly connected to a node in the local network space. In this case, the Node Address bits contain the processor ID of the local node connected to the destination node. Path creation means in said processor node compares the masked node address with its own processor ID and sends the address packet out the port number corresponding to the bit position of the first difference between the masked node address and its own processor ID, starting at bit n+1, where n is the number of the port on which the message was received.

    摘要翻译: 由多个节点组成的并行处理器网络,每个节点包括包含多个I / O端口的处理器和本地存储器。 网络中的每个处理器被分配唯一的处理器ID(202),使得通过端口号n彼此连接的两个处理器的处理器ID仅在第n位变化。 输入消息解码装置(200)并且比较逻辑和消息路由逻辑(204)响应于地址消息分组的解码而创建通过处理器的消息路径,并且响应于传输结束的解码而移除消息路径( EOT)数据包。 每个地址消息分组包括用于在网络内或外部网络向远程目的地发送消息的转发位。 每个地址分组包括包含目的地节点的处理器ID的节点地址位,目的地节点在本地网络中。 如果目标节点在外部网络空间中,目标节点必须直接连接到本地网络空间中的节点。 在这种情况下,节点地址位包含连接到目标节点的本地节点的处理器ID。 所述处理器节点中的路径创建装置将被屏蔽的节点地址与其自己的处理器ID进行比较,并从地址分组开始,将与掩蔽的节点地址和其自己的处理器ID之间的第一个差的位位置相对应的端口号发送给地址分组 +1,其中n是接收消息的端口的编号。

    High performance computer system
    3.
    发明授权
    High performance computer system 失效
    高性能计算机系统

    公开(公告)号:US5113523A

    公开(公告)日:1992-05-12

    申请号:US731170

    申请日:1985-05-06

    IPC分类号: G06F15/173

    CPC分类号: G06F15/17343

    摘要: A parallel processor comprised of a plurality of processing nodes (10), each node including a processor (100-114) and a memory (116). Each processor includes means (100, 102) for executing instructions, logic means (114) connected to the memory for interfacing the processor with the memory and means (112) for internode communication. The internode communication means (112) connect the nodes to form a first array (8) of order n having a hypercube topology. A second array (21) of order n having nodes (22) connected together in a hypercube topology is interconnected with the first array to form an order n+l array. The order n+l array is made up of the first and second arrays of order n, such that a parallel processor system may be structured with any number of processors that is a power of two. A set of I/O processors (24) are connected to the nodes of the arrays (8, 21) by means of I/O channels (106). The means for internode communication (112) comprises a serial data channel driven by a clock that is common to all of the nodes.

    摘要翻译: 一种由多个处理节点(10)组成的并行处理器,每个节点包括处理器(100-114)和存储器(116)。 每个处理器包括用于执行指令的装置(100,102),连接到存储器的用于将处理器与存储器接口的逻辑装置(114)和用于节点间通信的装置(112)。 节间通信装置(112)连接节点以形成具有超立方体拓扑的n阶的第一阵列(8)。 在超立方体拓扑中连接在一起的具有节点(22)的阶数为n的第二阵列(21)与第一阵列互连以形成阶n + l阵列。 顺序n + l阵列由阶数为n的第一和第二阵列组成,使得并行处理器系统可以被构造成具有两个幂的任意数目的处理器。 一组I / O处理器(24)通过I / O通道(106)连接到阵列(8,21)的节点。 用于节间通信的装置(112)包括由所有节点共同的时钟驱动的串行数据信道。

    Broadcast instruction for use in a high performance computer system
    4.
    发明授权
    Broadcast instruction for use in a high performance computer system 失效
    用于高性能计算机系统的广播指令

    公开(公告)号:US4729095A

    公开(公告)日:1988-03-01

    申请号:US864596

    申请日:1986-05-19

    摘要: A broadcast pointer instruction has a first source operand (address pointer value) which is the starting address in a memory of message data to be broadcast to a number of processors through output ports. The broadcast pointer instruction has a first destination operand (first multibit mask), there being one bit position in the first mask for each one of the plurality of output ports. The address pointer value is loaded into each of the output ports whose numbers correspond to bit positions in the first mask that are set to be one, such that each output port that is designated in the first mask receives the starting address of the message data in the memory. A broadcast count instruction has a second source operand (a byte count value) equal to the number of bytes in the message data. The broadcast count instruction has a second destination operand (a second multibit mask), there being one bit position in the second mask for each one of the plurality of output ports. The byte count value is sent to each of the output ports whose numbers correspond to bit positions in the second mask register that are set to be one, such that each output port that is designated in the second mask receives the byte count value corresponding to the number of bytes in the message data that are to be transferred from the memory. Once the byte count is initialized, data are transferred from the starting address in memory over each output port designated in the masks, until the byte count is decremented to zero.

    摘要翻译: 广播指针指令具有第一源操作数(地址指针值),其是要通过输出端口广播到多个处理器的消息数据的存储器中的起始地址。 广播指针指令具有第一目的地操作数(第一多位掩码),在多个输出端口中的每个输出端口的第一掩码中存在一个位位置。 地址指针值被加载到每个输出端口,其数量对应于第一掩码中的位位置被设置为1,使得在第一掩码中指定的每个输出端口接收消息数据的起始地址 记忆。 广播计数指令具有等于消息数据中的字节数的第二源操作数(字节计数值)。 广播计数指令具有第二目的地操作数(第二多位掩码),在多个输出端口中的每个输出端口的第二掩码中存在一位位置。 字节计数值被发送到每个输出端口,其数量对应于第二屏蔽寄存器中被设置为1的位位置,使得在第二掩码中指定的每个输出端口接收对应于 要从存储器传输的消息数据中的字节数。 一旦字节计数被初始化,数据从掩码中指定的每个输出端口的存储器中的起始地址传送,直到字节计数递减为零。