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    High performance computer system
    1.
    发明授权
    High performance computer system 失效
    高性能计算机系统

    公开(公告)号：US5113523A

    公开(公告)日：1992-05-12

    申请号：US731170

    申请日：1985-05-06

    申请人： Stephen R. Colley ,  David W. Jurasek ,  John F. Palmer ,  William S. Richardson ,  Doran K. Wilde

    发明人： Stephen R. Colley ,  David W. Jurasek ,  John F. Palmer ,  William S. Richardson ,  Doran K. Wilde

    IPC分类号： G06F15/173

    CPC分类号： G06F15/17343

    摘要： A parallel processor comprised of a plurality of processing nodes (10), each node including a processor (100-114) and a memory (116). Each processor includes means (100, 102) for executing instructions, logic means (114) connected to the memory for interfacing the processor with the memory and means (112) for internode communication. The internode communication means (112) connect the nodes to form a first array (8) of order n having a hypercube topology. A second array (21) of order n having nodes (22) connected together in a hypercube topology is interconnected with the first array to form an order n+l array. The order n+l array is made up of the first and second arrays of order n, such that a parallel processor system may be structured with any number of processors that is a power of two. A set of I/O processors (24) are connected to the nodes of the arrays (8, 21) by means of I/O channels (106). The means for internode communication (112) comprises a serial data channel driven by a clock that is common to all of the nodes.

    摘要翻译： 一种由多个处理节点（10）组成的并行处理器，每个节点包括处理器（100-114）和存储器（116）。 每个处理器包括用于执行指令的装置（100,102），连接到存储器的用于将处理器与存储器接口的逻辑装置（114）和用于节点间通信的装置（112）。 节间通信装置（112）连接节点以形成具有超立方体拓扑的n阶的第一阵列（8）。 在超立方体拓扑中连接在一起的具有节点（22）的阶数为n的第二阵列（21）与第一阵列互连以形成阶n + l阵列。 顺序n + l阵列由阶数为n的第一和第二阵列组成，使得并行处理器系统可以被构造成具有两个幂的任意数目的处理器。 一组I / O处理器（24）通过I / O通道（106）连接到阵列（8,21）的节点。 用于节间通信的装置（112）包括由所有节点共同的时钟驱动的串行数据信道。

    Numeric data processor
    3.
    再颁专利
    Numeric data processor 失效
    数字数据处理器

    公开(公告)号：USRE33629E

    公开(公告)日：1991-07-02

    申请号：US461538

    申请日：1990-06-01

    申请人： John F. Palmer ,  Bruce W. Ravenel ,  Rafi Nave

    发明人： John F. Palmer ,  Bruce W. Ravenel ,  Rafi Nave

    IPC分类号： G06F7/57 ,  G06F9/308 ,  G06F9/38 ,  G06F11/00

    CPC分类号： G06F9/3861 ,  G06F11/0763 ,  G06F7/483 ,  G06F9/30018 ,  G06F9/3885 ,  G06F7/4991 ,  G06F7/49947 ,  G06F7/49957 ,  G06F7/49963

    摘要： A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers, long or short integer words or BCD data upon which it must operate. As a result the circuit has a greater reliability, range and precision than ever previously achieved without entailing additional circuit complexity. Reliability is further enhanced by a systematic three bit rounding field, and by including means for detecting every error or exception condition with an optional expected response provided thereto by hardware. As a result of such organization, an unexpected increase of capacity is achieved wherein transcendental functions can be computed totally in hardware, and whereby mixed mode arithmetic can be implemented without difficulty. The numeric processor also includes a programmable shifter capable of arbitrary numbers of bit and byte shifts in a single clock cycle, as well as an arithmetic unit capable of implementing multiplication, division, modulo reduction and square roots directly in hardware.

    Numeric data processor
    4.
    发明授权
    Numeric data processor 失效
    数字数据处理器

    公开(公告)号：US4338675A

    公开(公告)日：1982-07-06

    申请号：US120995

    申请日：1980-02-13

    申请人： John F. Palmer ,  Bruce W. Ravenel ,  Rafi Nave

    发明人： John F. Palmer ,  Bruce W. Ravenel ,  Rafi Nave

    IPC分类号： G06F7/38 ,  G06F5/01 ,  G06F7/00 ,  G06F7/483 ,  G06F7/487 ,  G06F7/493 ,  G06F7/533 ,  G06F7/535 ,  G06F7/537 ,  G06F7/552 ,  G06F7/57 ,  G06F7/72 ,  G06F7/76 ,  G06F9/38 ,  G06F11/00 ,  G06F7/48 ,  G06F9/00

    CPC分类号： G06F9/3861 ,  G06F11/0763 ,  G06F5/012 ,  G06F7/483 ,  G06F7/5525 ,  G06F7/72 ,  G06F9/3877 ,  G06F7/4991 ,  G06F7/49947 ,  G06F7/49957 ,  G06F7/49963

    摘要： A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers, long or short integer words or BCD data upon which it must operate. As a result the circuit has a greater reliability, range and precision than ever previously achieved without entailing additional circuit complexity. Reliability is further enhanced by a systematic three bit rounding field, and by including means for detecting every error or exception condition with an optional expected response provided thereto by hardware. As a result of such organization, an unexpected increase of capacity is achieved wherein transcendental functions can be computed totally in hardware, and whereby mixed mode arithmetic can be implemented without difficulty. The numeric processor also includes a programmable shifter capable of arbitrary numbers of bit and byte shifts in a single clock cycle, as well as an arithmetic unit capable of implementing multiplication, division, modulo reduction and square roots directly in hardware.

    摘要翻译： 一个浮点集成运算电路围绕一个文件格式组织，该文件格式的浮点数字域超过任何单精度或双精度浮点数，长或短整数字或必须在其上运行的BCD数据。 因此，电路具有比以往更高的可靠性，范围和精度，而不需要额外的电路复杂性。 通过系统的三位舍入场进一步增强可靠性，并且包括用于通过硬件提供给其的可选择的预期响应来检测每个错误或异常状况的装置。 作为这种组织的结果，实现了能力的意外增加，其中可以在硬件中完全计算超越函数，并且可以毫无困难地实现混合模式运算。 数字处理器还包括能够在单个时钟周期中任意数量的位和字节移位的可编程移位器，以及能够直接在硬件中实现乘法，除法，模减减和平方根的算术单元。