公开(公告)号：US07024440B2

公开(公告)日：2006-04-04

申请号：US10806094

申请日：2004-03-23

申请人： Roberto B. Wiener

发明人： Roberto B. Wiener

IPC分类号： G06F17/10

CPC分类号： H03H17/0657 ,  G03F7/70725 ,  H03H17/0235 ,  H03H17/0621

摘要： A method and system of efficiently processing a discrete time input signal having a plurality of input signal samples that occur at a first clock rate into a discrete time output signal having a second clock rate that is R times the first clock rate is presented. The method includes receiving the input signal and filtering the input signal with an N-taps finite impulse response (FIR) filter having N filter coefficients. The method reduces the number of required operations and reduces computational errors in the filtering and interpolation of discrete input signals.

摘要翻译： 提出了一种有效处理具有以第一时钟速率发生的多个输入信号采样到离散时间输出信号的离散时间输入信号的方法和系统，其具有R倍于第一时钟速率的第二时钟速率。 该方法包括接收输入信号并用具有N个滤波器系数的N抽头有限脉冲响应（FIR）滤波器对输入信号进行滤波。 该方法减少了所需操作的数量，并减少了离散输入信号的滤波和内插中的计算误差。

公开(公告)号：US20040205425A1

公开(公告)日：2004-10-14

申请号：US10806325

申请日：2004-03-23

申请人： Silicon Valley Group, Inc. ,  ASML Holding N.V.

发明人： Roberto B. Wiener

IPC分类号： G06F017/17 ,  G11B005/00 ,  G06K005/04 ,  G11B020/20

CPC分类号： H03H17/0657 ,  G03F7/70725 ,  H03H17/0235 ,  H03H17/0621

摘要： A method and system of accurately processing a discrete time input signal having a first clock rate into a discrete time output signal having a second clock rate is presented. The method includes delta filtering the input signal to produce an intermediate signal having the first clock rate and delta interpolating the intermediate signal to produce the output signal. Delta filtering includes calculating an input delta signal by subtracting an initial value from the input signal, generating a filtered delta signal, and adding the initial value to the filtered delta signal. Delta interpolating includes upsampling the intermediate signal to the second clock rate, calculating an upsampled intermediate delta signal by subtracting an initial value from the upsampled intermediate signal, filtering the intermediate delta signal, and adding the initial value to the filtered intermediate delta signal. The method reduces the number of required operations and reduces computational errors in the filtering and interpolation of discrete input signals.

摘要翻译： 提出了一种将具有第一时钟速率的离散时间输入信号精确地处理成具有第二时钟速率的离散时间输出信号的方法和系统。 该方法包括对输入信号进行增量滤波以产生具有第一时钟速率的中间信号，并且对中间信号进行Δ内插以产生输出信号。 增量滤波包括通过从输入信号中减去初始值来计算输入增量信号，生成经滤波的增量信号，以及将初始值与滤波的增量信号相加。 增量插值包括将中间信号上采样到第二时钟速率，通过从上采样的中间信号中减去初始值，对中间增量信号进行滤波，并将初始值加到滤波后的中间增量信号上，计算上采样的中间增量信号。 该方法减少了所需操作的数量，并减少了离散输入信号的滤波和内插中的计算误差。

公开(公告)号：US06876698B1

公开(公告)日：2005-04-05

申请号：US09665884

申请日：2000-09-20

申请人： Christopher H. Dick ,  Frederic J. Harris

发明人： Christopher H. Dick ,  Frederic J. Harris

IPC分类号： H03H17/02 ,  H03H17/06 ,  H04B14/06 ,  H03H7/30

CPC分类号： H04B14/062 ,  H03H17/0235 ,  H03H17/0614 ,  H03H17/0621 ,  H03H2017/0692

摘要： A tunable narrow-band filter that includes a sigma-delta modulator. In one embodiment, a conventional DC canceler is modified to include a re-quantizer in the feedback loop in the form of a ΣΔ modulator. In another embodiment, a digital receiver employs a processing chip, such as an FPGA, that includes a ΣΔ modulator to requantize oversampled control signals in the digital receiver. In still another embodiment, a wide-bandwidth sigma-delta loop has a tunable center frequency.

摘要翻译： 包括Σ-Δ调制器的可调窄带滤波器。 在一个实施例中，常规DC消除器被修改为在SigmaDelta调制器形式的反馈环路中包括重新量化器。 在另一个实施例中，数字接收机采用诸如FPGA的处理芯片，其包括SigmaDelta调制器来对数字接收机中的过采样控制信号进行重新调整。 在另一个实施例中，宽带Σ-Δ环具有可调中心频率。

公开(公告)号：US06766339B2

公开(公告)日：2004-07-20

申请号：US09757622

申请日：2001-01-11

申请人： Roberto B. Wiener

发明人： Roberto B. Wiener

IPC分类号： G06F1710

CPC分类号： H03H17/0657 ,  G03F7/70725 ,  H03H17/0235 ,  H03H17/0621

摘要： The present invention is directed to efficient and accurate filtering and interpolation techniques. Methods of the present invention reduce the number of required operations and reduce computational errors in the filtering and interpolation of discrete input signals.

摘要翻译： 本发明涉及有效和准确的滤波和插值技术。 本发明的方法减少了所需操作的数量，并减少了离散输入信号的滤波和内插中的计算误差。

公开(公告)号：US20040177103A1

公开(公告)日：2004-09-09

申请号：US10806094

申请日：2004-03-23

申请人： Silicon Valley Group, Inc. ,  ASML US, Inc. to ASML Holding N.V.

发明人： Roberto B. Wiener

IPC分类号： G06F007/38

CPC分类号： H03H17/0657 ,  G03F7/70725 ,  H03H17/0235 ,  H03H17/0621

摘要： A method and system of efficiently processing a discrete time input signal having a plurality of input signal samples that occur at a first clock rate into a discrete time output signal having a second clock rate that is R times the first clock rate is presented. The method includes receiving the input signal and filtering the input signal with an N-taps finite impulse response (FIR) filter having N filter coefficients. The method reduces the number of required operations and reduces computational errors in the filtering and interpolation of discrete input signals.

摘要翻译： 提出了一种有效处理具有以第一时钟速率发生的多个输入信号采样到离散时间输出信号的离散时间输入信号的方法和系统，其具有R倍于第一时钟速率的第二时钟速率。 该方法包括接收输入信号并用具有N个滤波器系数的N抽头有限脉冲响应（FIR）滤波器对输入信号进行滤波。 该方法减少了所需操作的数量，并减少了离散输入信号的滤波和内插中的计算误差。

公开(公告)号：US06600788B1

公开(公告)日：2003-07-29

申请号：US09394123

申请日：1999-09-10

申请人： Christopher H. Dick ,  Frederic J. Harris

发明人： Christopher H. Dick ,  Frederic J. Harris

IPC分类号： H04B1406

CPC分类号： H04B14/062 ,  H03H17/0235 ,  H03H17/0614 ,  H03H17/0621 ,  H03H2017/0692

摘要： A narrow-band bandpass filter is implemented in a field programmable gate array (FPGA). An analog-to-digital converter quantizes an input analog signal with a high degree of precision to produce input data samples. A sigma-delta modulator re-quantizes the samples with a substantially lower degree of precision. The re-quantized samples are passed through a bandpass, lowpass, or highpass, finite impulse response (FIR) filter which operates at the lower degree of precision. The reduced degree of precision enables a substantial reduction in the number of resources required to implement the narrow-band bandpass, lowpass, or highpass filter in the FPGA. The modulator includes a predictor filter which has a center frequency coinciding with that of the FIR filter, and redistributes noise such that it is lowest within the passband of the FIR filter. The narrow-band filter design can be adapted to incorporate a single or multi-rate decimator configuration.

摘要翻译： 窄带带通滤波器在现场可编程门阵列（FPGA）中实现。 模数转换器以高精度量化输入模拟信号以产生输入数据采样。 Σ-Δ调制器以基本上较低的精度重新量化样品。 重新量化的样本通过以较低精度工作的带通，低通或高通，有限脉冲响应（FIR）滤波器。 精度降低能够大大减少在FPGA中实现窄带带通，低通或高通滤波器所需的资源数量。 调制器包括具有与FIR滤波器的中心频率一致的预测器滤波器，并且重新分布噪声，使得其在FIR滤波器的通带内是最低的。 窄带滤波器设计可以适应于采用单速率或多速率抽取器配置。

公开(公告)号：US4694413A

公开(公告)日：1987-09-15

申请号：US632467

申请日：1984-07-19

申请人： James H. Arbeiter

发明人： James H. Arbeiter

IPC分类号： H03H17/02 ,  G06F7/38

CPC分类号： H03H17/0235

摘要： The number of bits per digital sample that is required to be stored in each of one or more delay means of an input-weighted multitap digital filter is reduced with respect to that required by the prior art. The savings in storage hardware becomes more and more significant as the number of samples stored in each delay means becomes larger and larger. A plurality of filter delay means, each storing as many as 800 samples, are used in vertical filters of image processors operating in real time on horizontally scanned two-dimensional images, such as television images.

摘要翻译： 相对于现有技术所要求的，每个数字样本的每个数字样本的位数减少到输入加权多位数字滤波器的一个或多个延迟装置中的每一个中。 随着每个延迟装置中存储的样本数量越来越多，存储硬件的节省就变得越来越重要。 在水平扫描的二维图像（例如电视图像）上实时操作的图像处理器的垂直滤波器中使用多个滤波器延迟装置，每个滤波器延迟装置存储多达800个采样。

公开(公告)号：US07085793B2

公开(公告)日：2006-08-01

申请号：US10806325

申请日：2004-03-23

申请人： Roberto B. Wiener

发明人： Roberto B. Wiener

IPC分类号： G06F17/10

CPC分类号： H03H17/0657 ,  G03F7/70725 ,  H03H17/0235 ,  H03H17/0621

摘要： A method and system of accurately processing a discrete time input signal having a first clock rate into a discrete time output signal having a second clock rate is presented. The method includes delta filtering the input signal to produce an intermediate signal having the first clock rate and delta interpolating the intermediate signal to produce the output signal. Delta filtering includes calculating an input delta signal by subtracting an initial value from the input signal, generating a filtered delta signal, and adding the initial value to the filtered delta signal. Delta interpolating includes upsampling the intermediate signal to the second clock rate, calculating an upsampled intermediate delta signal by subtracting an initial value from the upsampled intermediate signal, filtering the intermediate delta signal, and adding the initial value to the filtered intermediate delta signal. The method reduces the number of required operations and reduces computational errors in the filtering and interpolation of discrete input signals.

摘要翻译： 提出了一种将具有第一时钟速率的离散时间输入信号精确地处理成具有第二时钟速率的离散时间输出信号的方法和系统。 该方法包括对输入信号进行增量滤波以产生具有第一时钟速率的中间信号，并且对中间信号进行Δ内插以产生输出信号。 增量滤波包括通过从输入信号中减去初始值来计算输入增量信号，生成经滤波的增量信号，以及将初始值与滤波的增量信号相加。 增量插值包括将中间信号上采样到第二时钟速率，通过从上采样的中间信号中减去初始值，对中间增量信号进行滤波，并将初始值加到滤波后的中间增量信号上，计算上采样的中间增量信号。 该方法减少了所需操作的数量，并减少了离散输入信号的滤波和内插中的计算误差。

公开(公告)号：US20030055855A1

公开(公告)日：2003-03-20

申请号：US09757622

申请日：2001-01-11

申请人： Silicon Valley Group, Inc.

发明人： Roberto B. Wiener

IPC分类号： G06F017/17

CPC分类号： H03H17/0657 ,  G03F7/70725 ,  H03H17/0235 ,  H03H17/0621

摘要： The present invention is directed to efficient and accurate filtering and interpolation techniques. Methods of the present invention reduce the number of required operations and reduce computational errors in the filtering and interpolation of discrete input signals.

摘要翻译： 本发明涉及有效和准确的滤波和插值技术。 本发明的方法减少了所需操作的数量，并减少了离散输入信号的滤波和内插中的计算误差。

公开(公告)号：US5572210A

公开(公告)日：1996-11-05

申请号：US218382

申请日：1994-03-25

申请人： Takashi Toyoda

发明人： Takashi Toyoda

IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H03M1/66

CPC分类号： H03H17/0235 ,  H03H17/0621

摘要： An apparatus for operating a digital signal includes a digital filter, a rounding process unit, a rounding error detecting unit and a rounding error eliminating unit. The allowable input word length is (m) bits for the digital filter. For the input with (n) bits which is longer than the allowable input word length of (m) bits, the rounding process unit processes the rounding and supplies it to the digital filter. The rounding error detecting unit extracts the rounding error based on the (n) bits input signal and the output signal after the rounding process. Utilizing this rounding error detected by the rounding error detecting unit, the rounding error eliminating unit eliminates the rounding error which has been mixed with the filtering output signal of the digital filter.

摘要翻译： 用于操作数字信号的装置包括数字滤波器，舍入处理单元，舍入误差检测单元和舍入误差消除单元。 数字滤波器的允许输入字长为（m）位。 对于具有比（m）位的允许输入字长长的（n）位的输入，舍入处理单元处理舍入并将其提供给数字滤波器。 舍入误差检测单元根据舍入处理后的（n）位输入信号和输出信号，提取舍入误差。 通过舍入误差检测部检测出的舍入误差，舍入误差消除部消除了与数字滤波器的滤波输出信号混合的舍入误差。