公开(公告)号：US6070180A

公开(公告)日：2000-05-30

申请号：US658999

申请日：1996-06-04

申请人： Toshiyuki Furusawa ,  Yusei Itaya ,  Masaru Ozeki

发明人： Toshiyuki Furusawa ,  Yusei Itaya ,  Masaru Ozeki

IPC分类号： G06F7/52 ,  G06P7/38

CPC分类号： G06F7/5324 ,  G06F2207/382

摘要： A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory (11) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit wiord length and the second arithmetic data string being composed of (m.times.n)-bits of a unit word length; two arithmetic operand storing registers (12) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle (13); and an arithmetic result storing register (15) for storing the arithmetic results outputted by said arithmetic logical unit.

摘要翻译： 公开了一种高速，高精度的数字信号处理器（DSP）。 DSP（即，数字运算集成电路）包括：运算数据存储存储器，用于存储运算数据，并在一个指令周期内输出由多个位组成的第一和第二运算数据串，第一运算 数据串由至少预定单位长度的m位组成，第二运算数据串由单位字长度的（m×n）位构成; 两个算术运算存储寄存器（12），用于分别存储由所述算术数据存储存储器输出的第一和第二算术数据串; 算术逻辑单元，用于在一个指令周期（13）中基于由所述算术运算存储寄存器输出的两个操作数执行算术运算; 以及用于存储由所述算术逻辑单元输出的算术结果的算术结果存储寄存器（15）。