公开(公告)号：US06389315B1

公开(公告)日：2002-05-14

申请号：US09513044

申请日：2000-02-25

申请人： Carl A. Schu ,  Daniel R. Greeninger ,  David L. Thompson

发明人： Carl A. Schu ,  Daniel R. Greeninger ,  David L. Thompson

IPC分类号： G61N1362

CPC分类号： A61N1/378 ,  A61N1/3627 ,  A61N1/3708

摘要： Improved operating system architecture for an implantable medical device incorporating self-timed logic for reducing power consumption and increasing and improving processing capabilities is disclosed. The self-timed logic is employed to implement digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages. The self-timed CMOS logic is incorporated into the same IC or ICs with clocked CMOS logic in a manner that minimizes the size of the clock tree serving the clocked CMOS logic, allows for efficient allocation of chip real estate, and provides manufacturing economies.