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    INTEGRATION OF SECURE DATA TRANSFER APPLICATIONS FOR GENERIC IO DEVICES
    1.
    发明申请
    INTEGRATION OF SECURE DATA TRANSFER APPLICATIONS FOR GENERIC IO DEVICES 审中-公开
    用于一般IO设备的安全数据传输应用的集成

    公开(公告)号：WO2009076405A1

    公开(公告)日：2009-06-18

    申请号：PCT/US2008/086168

    申请日：2008-12-10

    Applicant: SANDISK CORPORATION ,  LIU, Xian Jun ,  CHANG, Robert, C. ,  YUAN, Po ,  WANG, Junzhi ,  BARZILAI, Ron ,  QAWAMI, Bahman ,  SABET-SHARGHI, Farshid

    Inventor： LIU, Xian Jun ,  CHANG, Robert, C. ,  YUAN, Po ,  WANG, Junzhi ,  BARZILAI, Ron ,  QAWAMI, Bahman ,  SABET-SHARGHI, Farshid

    IPC: G06F3/06

    CPC classification number: G06F12/0886 ,  G06F12/0804 ,  G06F12/0871 ,  G06F12/0891 ,  G06F2212/1004 ,  G06F2212/1032 ,  G06F2212/2146 ,  G06F2212/462

    Abstract: Techniques are presented for sending an application instruction from a hosting digital appliance to a portable medium, where the instruction is structured as one or more units whose size is a first size, or number of bytes. After flushing the contents of a cache, the instruction is written to the cache, where the cache is structured as logical blocks having a size that is a second size that is larger (in terms of number of bytes) than the first size. In writing the instruction (having a command part and, possibly, a data part), the start of the instruction is aligned with one of the logical block boundaries in the cache and the instruction is padded out with dummy data so that it fills an integral number of the cache blocks. When a response from a portable device to an instruction is received at a hosting digital appliance, the cache is similarly flushed prior to receiving the response. The response is then stored to align with a logical block boundary of the cache.

    Abstract translation: 呈现用于将应用指令从主机数字设备发送到便携式介质的技术，其中指令被构造为大小为第一大小或字节数的一个或多个单元。 在刷新高速缓存的内容之后，该指令被写入高速缓存，其中高速缓存被构造为具有比第一大小更大（以字节数计）的第二大小的逻辑块。 在写入指令（具有命令部分和可能的数据部分）时，指令的开始与缓存中的逻辑块边界中的一个对齐，并且用虚拟数据填充指令，使得其填充积分 高速缓存块的数量。 当在主机数字设备处接收到从便携式设备到指令的响应时，高速缓存在接收到响应之前被类似地刷新。 然后存储响应以与高速缓存的逻辑块边界对齐。

    CONTROLLED DATA ACCESS TO NON-VOLATILE MEMORY
    4.
    发明申请
    CONTROLLED DATA ACCESS TO NON-VOLATILE MEMORY 审中-公开
    控制数据访问非易失性存储器

    公开(公告)号：WO2010074819A1

    公开(公告)日：2010-07-01

    申请号：PCT/US2009/063281

    申请日：2009-11-04

    Applicant: SANDISK CORPORATION ,  JOGAND-COULOMB, Fabrice ,  CHANG, Robert ,  YUAN, Po ,  YAN, Mei ,  LIU, Xian, Jun

    Inventor： JOGAND-COULOMB, Fabrice ,  CHANG, Robert ,  YUAN, Po ,  YAN, Mei ,  LIU, Xian, Jun

    IPC: G11C16/22 ,  G06F12/14 ,  G06F21/00 ,  G11C7/24

    CPC classification number: G11C16/22 ,  G06F13/4243 ,  G06F21/6218

    Abstract: A method of controlling data access to non-volatile memory is disclosed. The method includes storing a data file in a non-volatile memory. The non-volatile memory includes a memory array addressable by a plurality of address ranges one or more of which corresponding to a protected portion of the memory array and one or more of which corresponding to an unprotected portion of the memory array. The method also includes communicating to a host device an indication that a memory request with respect to the protected portion of the memory array is denied. The indication is communicated for instructing the host device to avoid a timeout.

    Abstract translation: 公开了一种控制对非易失性存储器的数据访问的方法。 所述方法包括将数据文件存储在非易失性存储器中。 非易失性存储器包括可由多个地址范围寻址的存储器阵列，其中一个或多个地址范围对应于存储器阵列的受保护部分，并且其中一个或多个对应于存储器阵列的未受保护部分。 所述方法还包括向主机设备传送关于存储器阵列的受保护部分的存储器请求被拒绝的指示。 传送指示以指示主机设备避免超时。

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