公开(公告)号：WO2013095639A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067213

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  HYUSEINOVA, Nevin ,  CAI, Qiong ,  OZDEMIR, Serkan ,  FALCON, Ayose J.

Inventor： HYUSEINOVA, Nevin ,  CAI, Qiong ,  OZDEMIR, Serkan ,  FALCON, Ayose J.

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G06F12/121 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/123 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/502

Abstract: Embodiments of the invention describe an apparatus, system and method for utilizing a utility and lifetime based cached replacement policy as described herein. For processors having one or more processor cores and a cache memory accessible via the processor core(s), embodiments of the invention describe a cache controller to determine, for a plurality of cache blocks in the cache memory, an estimated utility and lifetime of the contents of each cache block, the utility of a cache block to indicate a likelihood of use its contents, the lifetime of a cache block to indicate a duration of use of its contents. Upon receiving a cache access request resulting in a cache miss, said cache controller may select one of the cache blocks to be replaced based, at least in part, on one of the estimated utility or estimated lifetime of the cache block.

Abstract translation: 本发明的实施例描述了一种利用如本文所述的效用和基于生命周期的高速缓存替换策略的装置，系统和方法。 对于具有一个或多个处理器核心的处理器和经由处理器核心可访问的高速缓存存储器，本发明的实施例描述了一种高速缓存控制器，用于为高速缓冲存储器中的多个高速缓存块确定估计的效用和寿命 每个高速缓存块的内容，高速缓存块用于指示使用其内容的可能性的效用，高速缓存块的生命周期表示其内容的使用持续时间。 在接收到导致高速缓存未命中的高速缓存访​​问请求时，所述高速缓存控制器可以至少部分地基于高速缓存块的估计效用或估计的使用寿命之一来选择要替换的高速缓存块之一。

公开(公告)号：WO2013100975A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067611

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  OZDEMIR, Serkan ,  CAI, Qiong ,  FALCON, Ayose J. ,  HYUSEINOVA, Nevin

Inventor： OZDEMIR, Serkan ,  CAI, Qiong ,  FALCON, Ayose J. ,  HYUSEINOVA, Nevin

IPC: G06F12/02 ,  G06F13/16 ,  G11C13/02

CPC classification number: G06F12/06 ,  G06F12/0292 ,  G06F12/0646 ,  G06F13/16 ,  G06F2212/502 ,  G11C13/0004

Abstract: Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request to initialize a system memory including a plurality of memory banks. Using a plurality of memory address mapping schemes for memory settings for the system memory, a system characterization workload is executed during the initialization of the system memory, the system characterization workload including a plurality of transactions directed towards the system memory. Embodiments of the invention may monitor target addresses of the plurality of transactions directed towards the system memory. One of the plurality of memory address mapping schemes is selected based, at least in part, on the target addresses of the plurality of transactions.

Abstract translation: 本发明的实施例描述了用于工作负载自适应地址映射的装置，系统和方法。 本发明的实施例可以接收初始化包括多个存储体的系统存储器的请求。 使用用于系统存储器的存储器设置的多个存储器地址映射方案，在系统存储器的初始化期间执行系统表征工作负载，系统表征工作负载包括指向系统存储器的多个事务。 本发明的实施例可以监视针对系统存储器的多个事务的目标地址。 至少部分地基于多个事务的目标地址来选择多个存储器地址映射方案中的一个。

公开(公告)号：WO2013095644A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067221

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  HYUSEINOVA, Nevin ,  CAI, Qiong

Inventor： HYUSEINOVA, Nevin ,  CAI, Qiong

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/10 ,  G11C13/02

CPC classification number: G06F12/1027 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/202 ,  G06F2212/7211 ,  G11C16/3495

Abstract: Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (TLB). In response to determining the linear address is not included in the TLB, resulting in a TLB miss, embodiments of the invention may perform a page table walk to obtain a corresponding physical address, and convert the physical address to a device address for accessing the memory device based the tracked amount of writes. Thus, embodiments of the invention are more efficient compared to prior art solutions, as instead of all memory operations, only those that miss in the TLB incur additional wear leveling address translation overhead.

Abstract translation: 本发明的实施例描述了一种用于利用具有用于存储器件的磨损均衡逻辑/模块的页面未命中处理器的装置，系统和方法。 本发明的实施例可以跟踪针对存储器设备的单元的写入量，并且确定由系统写入事务指定的线性地址是否包括在翻译后备缓冲器（TLB）中。 响应于确定线性地址不包括在TLB中，导致TLB未命中，本发明的实施例可以执行页表移动以获得对应的物理地址，并将物理地址转换为用于访问存储器的设备地址 设备基于跟踪的写入量。 因此，与现有技术的解决方案相比，本发明的实施例更有效，而不是所有存储器操作，只有那些在TLB中错过的那些才能产生额外的损耗均衡地址转换开销。

公开(公告)号：WO2014143036A1

公开(公告)日：2014-09-18

申请号：PCT/US2013/032474

申请日：2013-03-15

Applicant: INTEL CORPORATION

Inventor： ZYULKYAROV, Ferad ,  HYUSEINOVA, Nevin ,  CAI, Qiong ,  CUESTA, Blas Bcuestax ,  OZDEMIR, Serkan ,  NICOLAIDES, Mario Marios

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/1045 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/126 ,  G06F2212/6022

Abstract: A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The method includes pinning the working set of a program into the requested memory (pin buffer) so that it is not evicted due to cache conflicts and is served from the fast cache and not the slower next level memory. The requested memory extends the physical address space and is visible to and managed by the OS. The OS has the ability to make the requested memory visible to the user programs. The OS has the ability to manage the requested memory from the far memory cache as both a fully associative cache and a set associative cache.

Abstract translation: 一种从远存储器高速缓存请求存储器并且在操作系统（OS）级别）实现所请求存储器上的完全关联高速缓存的方法。 该方法包括将程序的工作集锁定到请求的存储器（引脚缓冲器）中，使得它不会由于缓存冲突而被驱逐，并且从快速缓存而不是较慢的下一级存储器提供。 所请求的内存扩展了物理地址空间，并且由操作系统可见和管理。 操作系统能够使所请求的内存对用户程序可见。 操作系统能够将远程存储器缓存中所请求的存储器作为完全关联缓存和集合关联高速缓存进行管理。

公开(公告)号：WO2014051718A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/044804

申请日：2013-06-07

Applicant: INTEL CORPORATION

Inventor： CAI, Qiong ,  HYUSEINOVA, Nevin ,  OZDEMIR, Serkan ,  ZYULKYAROV, Ferad ,  NICOLAIDES, Marios ,  CUESTA, Blas

IPC: G06F1/00 ,  G06F13/14 ,  G06F12/08

CPC classification number: G06F12/126 ,  G06F12/0866 ,  G06F12/127 ,  G06F2212/214

Abstract: Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.

Abstract translation: 用于自动更改用于选择用于驱逐的缓存的行的替换策略之间的技术和机制。 在一个实施例中，评估逻辑确定用于写入非易失性存储器的性能度量的值。 基于确定的性能度量值，确定替换策略的参​​数值。 在另一个实施例中，高速缓存替换逻辑执行用于数据驱逐的高速缓存行的选择，其中所述选择是响应于策略单元提供所确定的参数值的指示。

公开(公告)号：WO2015148026A1

公开(公告)日：2015-10-01

申请号：PCT/US2015/017125

申请日：2015-02-23

Applicant: INTEL CORPORATION

Inventor： ROLAN, Dyer ,  HYUSEINOVA, Nevin ,  CUESTA, Blas A. ,  CAI, Qiong

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0871 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/122 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/502 ,  G06F2212/604 ,  G06F2212/62

Abstract: Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags stores a subset of tags stored by the tag storage. Where a tag of the first set is to be stored to the cache of cache tags, all tags of the first set are stored to the first portion. In another embodiment, any storage of tags of the first set to the cache of cache tags includes storage of the tags of the first set to only a first portion of the cache of cache tags. A replacement table is maintained for use in evicting or replacing cached tags based on an indicated level of activity for a set of the cache of cache tags.

Abstract translation: 在确定对缓存数据的访问时提供高速缓存标签缓存的技术和机制。 在一个实施例中，标签存储存储包括与高速缓冲存储器的相应数据位置相关联的标签的第一集合。 高速缓存标签的缓存存储标签存储器存储的标签的子集。 在将第一组的标签存储到高速缓存标签的高速缓存中的情况下，将第一组的所有标签存储到第一部分。 在另一个实施例中，将第一集合的标签的任何存储器存储到高速缓存标签的高速缓存包括将第一集合的标签仅存储在高速缓存标签的高速缓存的仅第一部分上。 维护一个替换表，用于根据一组高速缓存标签缓存的指定级别的活动逐出或替换高速缓存的标签。

公开(公告)号：WO2013147820A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031316

申请日：2012-03-29

Applicant: INTEL CORPORATION ,  ZYULKYAROV, Ferad ,  CAI, Qiong ,  HYUSEINOVA, Nevin ,  OZDEMIR, Serkan

Inventor： ZYULKYAROV, Ferad ,  CAI, Qiong ,  HYUSEINOVA, Nevin ,  OZDEMIR, Serkan

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F12/00 ,  G06F9/3004

Abstract: An apparatus and method for implementing non-volatile store (nvstore) and non-volatile flush (nvflush) instructions. For example, a method according to one embodiment comprises: executing a set of non-volatile store instructions indicating data to be persisted to a non-volatile memory (NVM) of a multi-level system memory hierarchy; generating an entry in an NVM store queue prior to storing the data to the NVM, each entry indicating that the data associated therewith has not yet been persisted to non-volatile memory; executing a non-volatile flush instruction at a time when the data associated with each entry in the non-volatile store queue should be persisted to non-volatile memory; and removing the entries from the NVM store queue as the data associated with each entry is written to non-volatile memory.

Abstract translation: 用于实现非易失性存储（nvstore）和非易失性flush（nvflush）指令的装置和方法。 例如，根据一个实施例的方法包括：执行指示要持久存储到多级系统存储器层级的非易失性存储器（NVM）的数据的一组非易失性存储指令; 在将数据存储到NVM之前，在NVM存储队列中生成条目，每个条目指示与其相关联的数据尚未被持久化到非易失性存储器; 在与非易失性存储队列中的每个条目相关联的数据应该被持久化到非易失性存储器时执行非易失性闪存指令; 并从NVM存储队列中删除条目，因为与每个条目关联的数据被写入非易失性存储器。

公开(公告)号：WO2013095641A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067218

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  HYUSEINOVA, Nevin ,  CAI, Qiong

Inventor： HYUSEINOVA, Nevin ,  CAI, Qiong

IPC: G06F12/06 ,  G06F13/16 ,  G11C13/02

CPC classification number: G06F12/10 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/7211 ,  G11C16/3495

Abstract: Embodiments of the invention describe an apparatus, system and method for sub-block based wear leveling for memory devices. Embodiments of the invention may receive a write request to a physical memory address including a physical block address and a physical sub-block address. An address remapping table is accessed to translate the physical block address to a memory device block address to locate a plurality of memory device sub-blocks. A plurality of sub-block activity counters are accessed, each sub-block activity counter associated with one of the memory device sub-blocks. One of the plurality of memory device sub-blocks is selected to store write data of the write request based, at least in part, on values of the plurality of sub-block activity counters, and the value of the sub-block activity counter associated with the selected memory device sub-block is updated.

Abstract translation: 本发明的实施例描述了一种用于存储器件的基于子块的磨损均衡的装置，系统和方法。 本发明的实施例可以接收对包括物理块地址和物理子块地址的物理存储器地址的写入请求。 访问地址重映射表以将物理块地址转换为存储器件块地址以定位多个存储器件子块。 访问多个子块活动计数器，每个子块活动计数器与存储器件子块之一相关联。 多个存储器件子块中的一个被选择为至少部分地基于多个子块活动计数器的值和相关联的子块活动计数器的值来存储写入请求的写入数据 所选择的存储器件子块被更新。