公开(公告)号：WO2020247211A1

公开(公告)日：2020-12-10

申请号：PCT/US2020/034579

申请日：2020-05-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SIMIONESCU, Horia C. ,  ADAMS, Lyle E. ,  XU, Yongcai ,  ISH, Mark

IPC: G06F12/0817 ,  G06F12/0853 ,  G06F12/0897 ,  G11C16/10 ,  G11C16/26

Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

公开(公告)号：WO2023069650A1

公开(公告)日：2023-04-27

申请号：PCT/US2022/047321

申请日：2022-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GUAN, Huapeng G. ,  SIMIONESCU, Horia C. ,  ZHU, Jiangli ,  PASALA, Venkata Naga Lakshman ,  WANG, Wei

IPC: G06F3/06

Abstract: A plurality of temperature values of the memory device is received. A temperature value of the plurality of temperature values that satisfies a thermal throttling threshold of a plurality of thermal throttling thresholds is determined, wherein each thermal throttling threshold of the plurality of thermal throttling thresholds triggers a corresponding thermal throttling state of the memory device. In response to determining that the temperature value satisfies the respective thermal throttling threshold, a thermal throttling operation associated with the corresponding thermal throttling state is performed.

公开(公告)号：WO2021055853A1

公开(公告)日：2021-03-25

申请号：PCT/US2020/051634

申请日：2020-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SIMIONESCU, Horia C. ,  CHIN, Chung Kuang ,  STONELAKE, Paul ,  KOTTE, Narasimhulu Dharanikumar

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/06 ,  G11C15/04

Abstract: Systems and methods are disclosed including a processing device operatively coupled to a first and a second memory device. The processing device can receive a set of data access requests, from a host system, in a first order and execute the set of data access requests in a second order. The processing device can further identify a late data access request of the set of data access requests and determine whether a data structure in a local memory associated with the processing device includes a previous outstanding data access request corresponding to an address associated with the late data access request. Responsive to determining that the data structure includes an indication of a previous outstanding data access request corresponding to the address associated with the late data access request, identifying a type of data dependency associated with the previous outstanding data access request and performing one or more operations associated with the type of data dependency.

公开(公告)号：WO2021055675A1

公开(公告)日：2021-03-25

申请号：PCT/US2020/051391

申请日：2020-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SIMIONESCU, Horia C. ,  CHIN, Chung Kuang ,  STONELAKE, Paul ,  KOTTE, Narasimhulu Dharanikumar

IPC: G06F13/16 ,  G06F12/06 ,  G06F3/06 ,  G06F12/0804 ,  G06F13/28 ,  G11C8/18 ,  G11C15/00

Abstract: Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device operatively coupled to the first and second memory components. The processing device can perform operations including receiving a data access operation and, responsive to determining that a data structure includes an indication of an outstanding data transfer of data associated with a physical address of the data access operation, determining whether an operation to copy the data, associated with the physical address, from the first memory component to the second memory component is scheduled to be executed. The processing device can further perform operations including determining to delay a scheduling of an execution of the data access operation until the operation to copy the data is executed.

公开(公告)号：WO2021055624A1

公开(公告)日：2021-03-25

申请号：PCT/US2020/051299

申请日：2020-09-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SIMIONESCU, Horia C. ,  STONELAKE, Paul ,  CHIN, Chung Kuang ,  KOTTE, Narasimhulu Dharanikumar ,  WALKER, Robert M. ,  DIRIK, Cagdas

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/06 ,  G06F12/123

Abstract: Systems and methods are disclosed including a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device operatively coupled to the first and second memory devices can track access statistics of segments of data stored at the second memory device, the segments having a first granularity, and determine to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the segment of data from the first memory device and store the additional data at the second memory device to form a new segment having the second granularity.