DOUBLE THRESHOLD CONTROLLED SCHEDULING OF MEMORY ACCESS COMMANDS

    公开(公告)号:WO2020176523A1

    公开(公告)日:2020-09-03

    申请号:PCT/US2020/019720

    申请日:2020-02-25

    Abstract: A processing device in a memory system provides an execution grant to a first queue of a plurality of queues, the first queue storing a first plurality of memory commands to be executed on the memory component. The processing device further determines whether a number of commands from the first queue that have been executed since the first queue received the execution grant satisfies an executed transaction threshold criterion and whether a number of pending commands in a second queue of the plurality of queues satisfies a promotion threshold criterion, the second queue storing a second plurality of memory commands to be executed on the memory component. Responsive to at least one of the executed transaction threshold criterion or the promotion threshold criterion being satisfied, the processing device provides the execution grant to the second queue.

    SCHEDULING OF READ OPERATIONS AND WRITE OPERATIONS BASED ON A DATA BUS MODE

    公开(公告)号:WO2020061092A1

    公开(公告)日:2020-03-26

    申请号:PCT/US2019/051579

    申请日:2019-09-17

    Abstract: A data bus can be determined to be in a write mode based on a prior operation transmitted over the data bus being a write operation. In response to determining that the data bus is in the write mode, a number of partition queues of a plurality of partition queues that include at least one write operation can be identified. A determination as to whether the number of partition queues of the plurality of partition queues satisfies a threshold number can be made. In response to determining that the number of partition queues satisfies the threshold number, another write operation from the plurality of partition queues can be transmitted over the data bus.

    HARDWARE BASED ACCELERATOR FOR MEMORY SUB-SYSTEM OPERATIONS

    公开(公告)号:WO2021011237A1

    公开(公告)日:2021-01-21

    申请号:PCT/US2020/041052

    申请日:2020-07-07

    Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can receive a first command for performing an operation on a set of management units. The acceleration engine can generate a set of one or more second commands to perform the operation on each management unit of the set of management units based on receiving the first command. The acceleration engine can perform the operation on each management unit of the set of management units based on generating the set of second commands.

    RESET AND REPLAY OF MEMORY SUB-SYSTEM CONTROLLER IN A MEMORY SUB-SYSTEM

    公开(公告)号:WO2021011201A1

    公开(公告)日:2021-01-21

    申请号:PCT/US2020/040557

    申请日:2020-07-01

    Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes host interface circuitry, middle logic, a media controller, and a media-controller restart manager that is configured to perform operations including detecting a triggering event for restarting the media controller, and responsively performing media-controller-restart operations that include suspending operation of the middle logic; determining whether the media controller is operating, and if so then suspending operation of the media controller; resetting the media controller; resuming operation of the media controller; and resuming operation of the middle logic.

    MANAGING THERMAL THROTTLING IN A MEMORY SUB-SYSTEM

    公开(公告)号:WO2023069650A1

    公开(公告)日:2023-04-27

    申请号:PCT/US2022/047321

    申请日:2022-10-20

    Abstract: A plurality of temperature values of the memory device is received. A temperature value of the plurality of temperature values that satisfies a thermal throttling threshold of a plurality of thermal throttling thresholds is determined, wherein each thermal throttling threshold of the plurality of thermal throttling thresholds triggers a corresponding thermal throttling state of the memory device. In response to determining that the temperature value satisfies the respective thermal throttling threshold, a thermal throttling operation associated with the corresponding thermal throttling state is performed.

    MANAGING POWER LOSS IN A MEMORY DEVICE
    7.
    发明申请

    公开(公告)号:WO2023034457A1

    公开(公告)日:2023-03-09

    申请号:PCT/US2022/042267

    申请日:2022-08-31

    Abstract: A system for managing power loss can include a number of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices. The processor can save a snapshot of a logical-to-physical (L2P) table to a non-volatile memory device and maintain a journal of updates of the L2P. The processor can, in response to a parameter of journal buffer of a volatile memory device satisfying a threshold criterion, save at least one journal of updates of the L2P table to the non-volatile memory device. It can also retrieve a sequence number from system metadata and save the most recent set of updates of the L2P table to a dedicated area of the non-volatile memory device, where the dedicated area is identified by the sequence number, in response to detecting a power loss event.

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