公开(公告)号：WO2022132538A1

公开(公告)日：2022-06-23

申请号：PCT/US2021/062467

申请日：2021-12-08

Applicant: RAMBUS INC.

Inventor： BAMDHAMRAVURI, Srinivas Satish Babu ,  WIJETUNGA, Panduka

IPC: G01R31/317 ,  G11C29/10 ,  G11C29/14 ,  G11C29/16

Abstract: Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of CA signals and the clock signal and the data interface outputs the pattern of CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representative of a timing offset between the clock signal and a sampling point for the first interface.