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    POWER MANAGER WITH A POWER SWITCH ARBITER
    1.
    发明申请
    POWER MANAGER WITH A POWER SWITCH ARBITER 审中-公开
    电源管理器与电源开关ARBITER

    公开(公告)号：WO2016201239A1

    公开(公告)日：2016-12-15

    申请号：PCT/US2016/036906

    申请日：2016-06-10

    Applicant: SONICS, INC.

    Inventor： EHMANN, Gregory ,  WINGARD, Drew, E. ,  WINGEN, Neal, T.

    IPC: G06F1/26

    CPC classification number: G06F1/3287 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/4403 ,  G06F13/37 ,  G06F13/4031 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/24

    Abstract: An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip, The arbitrator sequencing logic limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit, The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous eiectricai current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls behavior of power domains when powering up from multiple different behaviors.

    Abstract translation: 仲裁员控制不同功率域之间的仲裁，并对由芯片上的相同电源（VS）电路提供的不同功率域供电的序列进行管理。仲裁器排序逻辑限制了多少不同的功率域同时上电达到最大量， 小于在VS电路上画出的足够的瞬时电流，导致低于VS电路的最小可允许电源电压电平。排序逻辑通过考虑因素来管理对不同功率域供电的顺序i）是否不同 仲裁加电的功率域是共享VS电路的一组电源域的一部分，ii）所绘制的瞬时电流电流的量，以及iii）在发生最小允许电源电压电平之前可用的信用量 VS-电路。 排序逻辑控制从多个不同行为上电时电源域的行为。

    SCALABLE CACHE COHERENCE FOR A NETWORK ON A CHIP
    2.
    发明申请
    SCALABLE CACHE COHERENCE FOR A NETWORK ON A CHIP 审中-公开

    公开(公告)号：WO2013177295A3

    公开(公告)日：2013-11-28

    申请号：PCT/US2013/042251

    申请日：2013-05-22

    Applicant: SONICS, INC.

    Inventor： JAYASHIMHA, Doddaballapur, N. ,  WINGARD, Drew, E.

    IPC: G06F12/08

    Abstract: Maintaining cache coherence in a System-on-a-Chip with both multiple cache coherent master IP cores (CCMs) and non-cache coherent master IP cores (NCMs). A plug-in cache coherence manager (CM), coherence logic in agents, and an interconnect are used for the SoC to provide a scalable cache coherence scheme that scales to an amount of CCMs in the SoC. The CCMs each includes at least one processor operatively coupled through the CM to at least one cache that stores data for that CCM. The CM maintains cache coherence responsive to a cache miss of a cache line on a first cache of the caches, then broadcasts a request for an instance of the data stored corresponding to cache miss of the cache line in the first cache. Each CCM maintains its own coherent cache and each NCM is configured to issue communication transactions into both coherent and non-coherent address spaces.

    APPARATUS AND METHODS TO CONCURRENTLY PERFORM PER-THREAD AND PER-TAG MEMORY ACCESS
    4.
    发明申请
    APPARATUS AND METHODS TO CONCURRENTLY PERFORM PER-THREAD AND PER-TAG MEMORY ACCESS 审中-公开
    同时执行PER-THREAD和PER-TAG MEMORY ACCESS的设备和方法

    公开(公告)号：WO2012018465A1

    公开(公告)日：2012-02-09

    申请号：PCT/US2011/042513

    申请日：2011-06-30

    Applicant: SONICS, INC. ,  SRINIVASAN, Krishnan ,  KHAZHAKYAN, Ruben ,  ASLANYAN, Harutyun ,  WINGARD, Drew, E. ,  CHOU, Chien-chun

    Inventor： SRINIVASAN, Krishnan ,  KHAZHAKYAN, Ruben ,  ASLANYAN, Harutyun ,  WINGARD, Drew, E. ,  CHOU, Chien-chun

    IPC: G06F13/00 ,  G06F1/10

    CPC classification number: G06F9/526 ,  G06F12/0879 ,  G06F12/0882

    Abstract: A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

    Abstract translation: 集成电路包括启动器知识产权（IP）核心，目标IP核，互连以及标签和线程逻辑的方法，装置和系统。 目标IP核可以包括耦合到发起者IP核的存储器。 另外，互连可以允许集成电路在一个或多个启动器知识产权（IP）核心和耦合到互连的一个或多个目标IP核之间传送事务。 标签和线程逻辑可以被配置为同时执行线程内和跨多个线程的每线程和每标签内存访问调度，使得标签和线程逻辑管理标签和线程以允许每标签和每个线程调度 的内存从发起者IP内核访问来自发起者IP核的请求的初始发布顺序的顺序的请求。

    AN OPERATING POINT CONTROLLER FOR CIRCUIT REGIONS IN AN INTEGRATED CIRCUIT
    8.
    发明申请
    AN OPERATING POINT CONTROLLER FOR CIRCUIT REGIONS IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：WO2018165111A1

    公开(公告)日：2018-09-13

    申请号：PCT/US2018/021076

    申请日：2018-03-06

    Applicant: SONICS, INC.

    Inventor： EHMANN, Gregory ,  WINGARD, Drew, E.

    IPC: G06F1/26 ,  G05F3/02 ,  G06F1/04

    Abstract: In an embodiment, an operating point controller for two or more circuit regions in an integrated circuit is discussed. The OPC is configured to both i) set a resource state, including operating voltage and operating frequency, for each of those circuit regions, and ii) identify events to initiate transitions between two or more operating points for a given circuit region. The operating point controller is also configured to manage transitions between operating points for the two or more circuit regions on the integrated circuit. The operating point controller is a hardware based machine implemented in logic rather than software operating on a CPU processor.

    METHODS AND APPARATUS FOR VIRTUALIZATION IN AN INTEGRATED CIRCUIT
    9.
    发明申请
    METHODS AND APPARATUS FOR VIRTUALIZATION IN AN INTEGRATED CIRCUIT 审中-公开
    集成电路虚拟化的方法和设备

    公开(公告)号：WO2012061700A1

    公开(公告)日：2012-05-10

    申请号：PCT/US2011/059316

    申请日：2011-11-04

    Applicant: SONICS, INC. ,  WINGARD, Drew, E.

    Inventor： WINGARD, Drew, E.

    IPC: G06F9/455

    CPC classification number: G06F12/1027

    Abstract: Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. A centralized Memory Management logic Unit (MMU) is located in the interconnect for virtualization and sharing of integrated circuit resources including target cores between the one or more initiator IP cores. A master translation look aside buffer (TLB) stores virtualization and sharing information in the entries of the master TLB. A set of two or more translation look aside buffers (TLBs) locally store virtualization and sharing information replicated from the master TLB. Logic in the MMU or other software updates the virtualization and sharing information replicated from the master TLB in the entries of one or more of the set of local TLBs.

    Abstract translation: 描述了用于在一个或多个发起者IP核与耦合到互连的一个或多个目标IP核之间进行交易的各种方法和装置。 集成的内存管理逻辑单元（MMU）位于互连中，用于集成电路资源的虚拟化和共享，包括一个或多个启动器IP内核之间的目标内核。 主翻译看缓冲区（TLB）将虚拟化和共享信息存储在主TLB的条目中。 一组两个或更多的翻译旁边缓冲区（TLB）本地存储从主TLB复制的虚拟化和共享信息。 MMU或其他软件中的逻辑更新在主TLB中的一个或多个本地TLB的条目中复制的虚拟化和共享信息。

    VARIOUS METHODS AND APPARATUSES FOR OPTIMIZING CONCURRENCY IN MULTIPLE CORE SYSTEMS
    10.
    发明申请
    VARIOUS METHODS AND APPARATUSES FOR OPTIMIZING CONCURRENCY IN MULTIPLE CORE SYSTEMS 审中-公开
    在多核心系统中优化相似度的各种方法和设备

    公开(公告)号：WO2011109305A1

    公开(公告)日：2011-09-09

    申请号：PCT/US2011/026513

    申请日：2011-02-28

    Applicant: SONICS, INC. ,  JAYASIMHA, Doddaballapur, N. ,  TON, Luc, Hoa ,  WINGARD, Drew, E.

    Inventor： JAYASIMHA, Doddaballapur, N. ,  TON, Luc, Hoa ,  WINGARD, Drew, E.

    IPC: G06F9/46

    CPC classification number: G06F15/173

    Abstract: Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. Tag logic may be located within the interconnect, such as located in an agent, and configured to assign different interconnect tag identification numbers to two or more transactions from a same thread. The tag logic assigns different interconnect tag identification numbers to allow the two or more transactions from the same thread to be outstanding over the interconnect to two or more different target IP cores at the same time, allow the two or more transactions from the same thread to be processed in parallel over the interconnect, and potentially serviced out of issue order while being returned back to the multiple threaded initiator IP core realigned in expected execution order.

    Abstract translation: 描述了用于在一个或多个发起者IP核与耦合到互连的一个或多个目标IP核之间进行交易的各种方法和装置。 标签逻辑可以位于互连中，例如位于代理中，并且被配置为将不同的互连标签标识号分配给来自同一线程的两个或多个事务。 标签逻辑分配不同的互连标签标识号，以允许来自同一线程的两个或更多个事务在互连上同时在两个或多个不同的目标IP核之间是突出的，允许来自相同线程的两个或更多个事务 通过互连并行处理，并且可能在出现问题顺序的情况下被服务，同时返回到按预期执行顺序重新排列的多线程启动器IP内核。

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