公开(公告)号：WO2014106040A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/077975

申请日：2013-12-27

Applicant: SYNOPSYS, INC.

Inventor： LIN, Yan ,  JIANG, Yi-Min ,  TAI, Phillip H. ,  YUAN, Lin

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules.

Abstract translation: 描述了基于模式的电力和地面（PG）路由以及基于通过创建的基于规则的系统和技术。 可以接收用于布线PG导线的图案。 接下来，可以接收实例化策略，其中所述实例化策略指定集成电路（IC）设计布局的区域，其中基于所述模式的PG线将被实例化，并且指定将被分配给所述模式的一个或多个净标识符 实例化的PG线。 PG线可以根据模式和实例化策略在IC设计布局中实例化。 另外，可以接收一组通孔规则，其中每个通孔规则指定要在两个不同金属层中的两条PG线之间的交点处要实例化的通孔类型。 接下来，可以基于一组通孔规则在IC设计布局中实例化一个或多个通孔。

公开(公告)号：WO2014105980A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/077856

申请日：2013-12-26

Applicant: SYNOPSYS, INC.

Inventor： PEART, David L. ,  LIN, Yan ,  LU, Aiguo ,  RASHINGKAR, Balkrishna R. ,  SEGAL, Russell B. ,  ZOU, Peiqing

IPC: G06F17/50 ,  G06F1/04

CPC classification number: G06F17/5072 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

Abstract: Techniques and systems for performing clock tree synthesis (CTS) across multiple modes are described. Some embodiments traverse one or more clock trees from the root of each clock tree to a set of sinks of the clock tree. During the traversal, each clock gate can be marked with a traversal level, and each sink can be marked with one or more clocks and one or more modes that are associated with the sink. A task queue can then be created based on the information collected during the clock tree traversal and populated with different types of tasks based on skew balancing requirements across different modes, and the task queue can be provided to a CTS engine to achieve high-quality skew-balanced clock trees across all modes.

Abstract translation: 描述了跨多个模式执行时钟树合成（CTS）的技术和系统。 一些实施例将一个或多个时钟树从每个时钟树的根遍历到时钟树的一组汇集。 在遍历期间，每个时钟门可以标记遍历级别，每个接收器可以标记一个或多个时钟和一个或多个与接收器相关联的模式。 然后可以基于在时钟树遍历期间收集的信息创建任务队列，并根据跨不同模式的偏差平衡要求填充不同类型的任务，并且可以将任务队列提供给CTS引擎以实现高质量的偏移 平衡时钟树在所有模式。

公开(公告)号：WO2014105938A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/077779

申请日：2013-12-26

Applicant: SYNOPSYS, INC.

Inventor： PEART, David L. ,  LIN, Yan ,  LU, Aiguo ,  RASHINGKAR, Balkrishna R. ,  SEGAL, Russell B. ,  ZOU, Peiqing

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

Abstract: Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.

Abstract translation: 描述了其中整形与用于电网（PG）对准的电力网络合成（PNS）集成的实施例。 具体地，一些实施例基于期望由PNS创建的PG创建布局约束，然后基于布局约束对电路设计进行整形（或执行合法化）。 这确保在成形期间物理分区（例如，多实例化块的实例）与电网对齐。

公开(公告)号：WO2010085284A1

公开(公告)日：2010-07-29

申请号：PCT/US2009/055627

申请日：2009-09-01

Applicant: SYNOPSYS, INC. ,  LIN, Yan ,  JIANG, Yi-Min ,  YUAN, Lin

Inventor： LIN, Yan ,  JIANG, Yi-Min ,  YUAN, Lin

IPC: G06F19/00 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

Abstract: A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.

Abstract translation: 提供了一种在集成电路（IC）的电力网络中最小化电压降的同时自动减少堆叠通孔的方法。 在该方法中，可以虚拟地去除电力网络的任何可行的（即，不是连通性必需的和未占用的堆叠通孔）堆叠的通孔。 如果超过电力网络的目标电压降，则可以更新IC上至少最大电压降的严重程度。 在该更新之后，可以将一组降压改进的堆叠过孔实际返回给电力网络。 可以重复确定是否超过目标电压降的步骤，更新一个或多个热点处的电压降的严重性，以及实际返回该组附加堆叠通孔的步骤，直到不超过目标电压降。