公开(公告)号：WO2016057883A2

公开(公告)日：2016-04-14

申请号：PCT/US2015054864

申请日：2015-10-09

Applicant: TEXAN INSTR INC ,  TEXAS INSTRUMENTS JAPAN

Inventor： J DIVYASREE ,  KAMATH ANANT SHANKAR

IPC: H03L7/00

CPC classification number: H03L7/06 ,  H03K3/0231 ,  H03K3/0315 ,  H03K4/06 ,  H03L7/00

Abstract: In described examples, an FLL (frequency locked loop) oscillator/clock generator (100) includes a free-running oscillator (110), which generates an FLL clk with an FLL-controlled frequency fosc- The FLL control loop includes a switched capacitor resistor divider (130) that converts fosc to a resistance, generating an FLL feedback voltage (Vfosc) to generate a loop control signal (OSC cntrl) input to the oscillator (110). In response, the oscillator frequency locks FLL clk to fosc. In an example implementation, the FLL oscillator/clock generator (100) operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

Abstract translation: 在所描述的示例中，FLL（锁频环）振荡器/时钟发生器（100）包括自由振荡器（110），其产生具有FLL控制频率fosc的FLL clk。FLL控制回路包括开关电容电阻器 分频器（130），其将fosc转换成电阻，产生FLL反馈电压（Vfosc）以产生输入到振荡器（110）的回路控制信号（OSC cntr1）。 作为响应，振荡器频率将FLL clk锁定到fosc。 在一个示例实现中，FLL振荡器/时钟发生器（100）以扩展频谱时钟（SSC）工作，该扩频频谱时钟（SSC）基于作为对RC弛豫振荡器的负反馈而产生的截断RC转换电压提供三角形SSC调制，其基于切换 跳闸阈值电压产生正向反馈到RC松弛振荡器。