公开(公告)号：WO2017124094A1

公开(公告)日：2017-07-20

申请号：PCT/US2017/013768

申请日：2017-01-17

Applicant: SEAMLESS DEVICES, INC.

Inventor： KUPPAMBATTI, Jayanth

IPC: H03K3/00 ,  H03F3/00 ,  H03F3/45 ,  H03K3/02

CPC classification number: H03F1/0205 ,  H03F1/56 ,  H03F3/193 ,  H03F3/21 ,  H03F3/45179 ,  H03F2200/387 ,  H03F2200/451 ,  H03K3/0315 ,  H03K3/0322

Abstract: An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs and a second oscillator having an input and N outputs. The amplifier includes N phase detectors, each phase detector has a first input, a second input, a first output, and a second output, where each first input of each phase detector is coupled to respective one of the N outputs of the first oscillator, where each second input of each phase detector is coupled to respective one of the N outputs of the second oscillator. The amplifier includes N quantizers, each quantizer has a data input, a clock input, and an output, where each data input of each quantizer is coupled to respective one first output or one second output of the N phase detectors.

Abstract translation: 一种面积有效的放大器，用于放大连续时间连续幅度信号并将其转换为离散时间离散幅度信号。 放大器包括具有输入和多个N输出的第一振荡器以及具有输入和N输出的第二振荡器。 该放大器包括N个相位检测器，每个相位检测器具有第一输入，第二输入，第一输出和第二输出，其中每个相位检测器的每个第一输入耦合到第一振荡器的N个输出中相应的一个， 其中每个相位检测器的每个第二输入端耦合到第二振荡器的N个输出端中的相应一个输出端。 该放大器包括N个量化器，每个量化器具有数据输入，时钟输入和输出，其中每个量化器的每个数据输入端耦合到N个相位检测器的相应一个第一输出或一个第二输出。

公开(公告)号：WO2016205630A2

公开(公告)日：2016-12-22

申请号：PCT/US2016/038055

申请日：2016-06-17

Applicant: MARVELL WORLD TRADE LTD. ,  YAYLA, Mustafa, Oguzhan ,  GAO, Xiang ,  LIN, Li

Inventor： YAYLA, Mustafa, Oguzhan ,  GAO, Xiang ,  LIN, Li

IPC: H03B19/14

CPC classification number: H03K5/00006 ,  H03B19/14 ,  H03B2200/007 ,  H03B2202/05 ,  H03K3/0315

Abstract: A system includes a signal generator and a signal combiner. The signal generator is configured to output a first signal having a first frequency and to output one or more signals having the first frequency and having phases shifted relative to the first signal by predetermined amounts. The signal combiner is configured to combine the first signal and the one or more signals to output a frequency multiplied second signal having a second frequency. The second frequency is greater than the first frequency.

Abstract translation: 系统包括信号发生器和信号组合器。 信号发生器被配置为输出具有第一频率的第一信号，并输出具有第一频率的一个或多个信号，并且具有相对于第一信号相移一定预定量的相位。 信号组合器被配置为组合第一信号和一个或多个信号以输出具有第二频率的倍频的第二信号。 第二个频率大于第一个频率。

公开(公告)号：WO2016182676A1

公开(公告)日：2016-11-17

申请号：PCT/US2016/027627

申请日：2016-04-14

Applicant: QUALCOMM INCORPORATED

Inventor： LIU, Chunchen ,  LAW, Oscar Ming Kin ,  LU, Ju-Yi ,  CHEN, Po-Hung ,  DUAN, Zhengyu

IPC: G01R31/3193 ,  H03K3/03 ,  H03K19/003

CPC classification number: H03K3/0315 ,  G01R31/31937 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/11807 ,  H03K3/012 ,  H03K19/00346

Abstract: Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal (410) produced by a first ring oscillator (404) that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit (406, 408) that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit (406, 408), and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal (410) produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal (410) when the second ring oscillator circuit is operated in the second mode.

Abstract translation: 描述了与用于制造半导体IC器件的参数和指导相关的方法和装置。 一种方法包括测量由第一环形振荡器（404）产生的第一振荡信号（410），所述第一振荡信号包括设置在IC的第一互连层中的第一互连，为第二环形振荡器电路选择第一工作模式（406， 408），其包括与所述第一互连对准布置的第二互连，为所述第二环形振荡器电路（406,408）选择第二工作模式，以及基于所述第一互连的频率差来确定所述第一互连的一个或多个特性 当第二环形振荡器电路在第二模式下操作时，当第二环形振荡器电路以第一模式操作时产生的第一振荡信号（410）和第一振荡信号（410）的频率产生。

公开(公告)号：WO2016057883A2

公开(公告)日：2016-04-14

申请号：PCT/US2015054864

申请日：2015-10-09

Applicant: TEXAN INSTR INC ,  TEXAS INSTRUMENTS JAPAN

Inventor： J DIVYASREE ,  KAMATH ANANT SHANKAR

IPC: H03L7/00

CPC classification number: H03L7/06 ,  H03K3/0231 ,  H03K3/0315 ,  H03K4/06 ,  H03L7/00

Abstract: In described examples, an FLL (frequency locked loop) oscillator/clock generator (100) includes a free-running oscillator (110), which generates an FLL clk with an FLL-controlled frequency fosc- The FLL control loop includes a switched capacitor resistor divider (130) that converts fosc to a resistance, generating an FLL feedback voltage (Vfosc) to generate a loop control signal (OSC cntrl) input to the oscillator (110). In response, the oscillator frequency locks FLL clk to fosc. In an example implementation, the FLL oscillator/clock generator (100) operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

Abstract translation: 在所描述的示例中，FLL（锁频环）振荡器/时钟发生器（100）包括自由振荡器（110），其产生具有FLL控制频率fosc的FLL clk。FLL控制回路包括开关电容电阻器 分频器（130），其将fosc转换成电阻，产生FLL反馈电压（Vfosc）以产生输入到振荡器（110）的回路控制信号（OSC cntr1）。 作为响应，振荡器频率将FLL clk锁定到fosc。 在一个示例实现中，FLL振荡器/时钟发生器（100）以扩展频谱时钟（SSC）工作，该扩频频谱时钟（SSC）基于作为对RC弛豫振荡器的负反馈而产生的截断RC转换电压提供三角形SSC调制，其基于切换 跳闸阈值电压产生正向反馈到RC松弛振荡器。

公开(公告)号：WO2016044057A1

公开(公告)日：2016-03-24

申请号：PCT/US2015/049427

申请日：2015-09-10

Applicant: INTEL CORPORATION

Inventor： FAMILIA, Noam ,  SAKSONOV, Avigdor ,  FAYNEH, Eyal ,  SHOR, Joseph

IPC: H03L7/099 ,  H03L7/14

CPC classification number: H03L7/0991 ,  H03B5/10 ,  H03K3/0315 ,  H03L5/00 ,  H03L7/083 ,  H03L7/091 ,  H03L7/093 ,  H03L7/095 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18

Abstract: Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.

Abstract translation: 一些实施例包括在数字锁相环（PLL）和控制环路中具有数字控制振荡器（DCO）的装置和方法。 DCO可以产生具有基于数字信息的值的频率的输出信号。 控制回路可以根据数字信息的值调节DCO的电源电压值。 描述附加的装置和方法。

公开(公告)号：WO2011071545A3

公开(公告)日：2015-07-09

申请号：PCT/US2010020154

申请日：2010-01-05

Applicant: ESS TECHNOLOGY INC ,  MALLINSON ANDREW MARTIN

Inventor： MALLINSON ANDREW MARTIN

IPC: H03L7/08

CPC classification number: G05B11/40 ,  H03F3/45183 ,  H03F2203/45166 ,  H03F2203/45224 ,  H03F2203/45674 ,  H03K3/0315 ,  H03L7/093 ,  H03L7/0995

Abstract: Multi-phase integrators in control systems are described.

Abstract translation: 描述控制系统中的多相积分器。

公开(公告)号：WO2015014114A1

公开(公告)日：2015-02-05

申请号：PCT/CN2014/071614

申请日：2014-01-28

Applicant: 浙江大学

Inventor： 韩雁 ,  孙俊 ,  刘晓鹏 ,  钱雨霁

IPC: H03B5/04

CPC classification number: H03L7/24 ,  H03K3/011 ,  H03K3/0315

Abstract: 本发明公开了一种抗工艺涨落的自修调片上振荡器，包括集成于同一芯片的用于产生基准脉冲的基准振荡单元，用于产生输出脉冲的待修调振荡单元，以及用于接收基准脉冲和输出脉冲，并根据接收到的基准脉冲和输出脉冲向待修调振荡单元发出相应的修调信号，控制待修调振荡单元对输出脉冲进行频率修调的自修调逻辑控制单元。由可片内集成的基准振荡单元提供频率调修所需的基准脉冲，并在修调完成后关闭基准振荡单元，实现了输出频率的片内自修调，避免片外修调，有利于降低芯片制备成本。且硬件结构简单，容易实现，并在不修调时，关闭基准振荡单元，降低芯片的功耗。

公开(公告)号：WO2015008067A1

公开(公告)日：2015-01-22

申请号：PCT/GB2014/052175

申请日：2014-07-16

Applicant: PRAGMATIC PRINTING LTD

Inventor： DE OLIVEIRA, Joao ,  WHITE, Scott Darren ,  RAMSDALE, Catherine

IPC: H03K19/0944

CPC classification number: H03K19/0944 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/356017 ,  H03K17/16 ,  H03K19/09441 ,  H03K19/20 ,  H03K23/002

Abstract: An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.

Abstract translation: 电子电路包括：输入端; 输出端子; 第一和第二供电轨; 第一，第二，第三和第四场效应晶体管，每个具有第一类型和每个具有相应的栅极，源极和漏极端子的FET; 以及第一和第二载荷。 第一FET的源极连接到第一电源轨，第一FET的漏极和第二FET的源极连接到输出端子，第二FET的漏极连接到第二电源轨，栅极 第三FET的栅极和第四FET的栅极连接到输入端子，第三FET的漏极连接到第二电源轨，第一负载连接在第一电源轨和第三FET的源极之间， 并且第二负载连接在第四FET的漏极和第二电源轨之间。 在本发明的一个方面，第一FET的栅极连接到第三FET的源极与第一负载之间的节点，使得第三FET的源极处的电压被施加到第一FET的栅极， 并且第二FET的栅极连接到第四FET的漏极和第二负载之间的节点，使得第四FET的漏极处的电压被施加到第二FET的栅极。

公开(公告)号：WO2014120416A3

公开(公告)日：2014-10-23

申请号：PCT/US2014011181

申请日：2014-01-11

Applicant: QUALCOMM INC

Inventor： KHALILI ALIREZA

IPC: H03K3/03 ,  H01L29/423 ,  H03K3/354 ,  H03K3/3562

CPC classification number: H03K3/35625 ,  H03K3/0315 ,  H03K3/354

Abstract: A divide-by-two divider circuit receives a differential input signal and outputs four rail-to-rail, twenty-five percent duty cycle signals, where the frequency of the output signals is half of the frequency of the input signal. Each latch can output its output signals into loads of at least 15fF at a frequency of at least 3GHz so that each output signal has a phase noise of better than 160dBc/Hz, while the latch consumes less than 0.7mW over PVT from a supply voltage less than 1.0 volt. Each latch has a cross-coupled pair of P-channel transistors and two output signal generating branches. A static current blocking circuit in each branch prevents current flow in the branch during times when the branch is not switching its output signal. The input node of the latch is capacitively coupled to a signal source, and the DC voltage on the node is set by a bias circuit.

Abstract translation: 除二分频器电路接收差分输入信号并输出​​四个轨到轨，百分之二十五的占空比信号，其中输出信号的频率是输入信号频率的一半。 每个锁存器可以以至少3GHz的频率将其输出信号输出到至少15fF的负载，使得每个输出信号具有优于160dBc / Hz的相位噪声，而锁存器从电源电压消耗比PVT小0.7mW 小于1.0伏特。 每个锁存器都有一对交叉耦合的P沟道晶体管和两个输出信号生成分支。 每个分支中的静态电流阻塞电路在分支不切换其输出信号的时间内防止分支中的电流流动。 锁存器的输入节点电容耦合到信号源，节点上的直流电压由偏置电路设置。

公开(公告)号：WO2014150615A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/023792

申请日：2014-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Zhu, Yunliang ,  Tang, Yiwu

IPC: H03K3/03

CPC classification number: H03L7/00 ,  H03B19/14 ,  H03B27/00 ,  H03K3/0315 ,  H03K3/0322 ,  H03L7/18 ,  H03L7/24 ,  H04B1/40

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置产生LO信号。 该装置包括耦合在一起的LO发生器模块和注入信号发生器模块。 LO发生器模块具有多个LO输出和多个注入信号输入。 LO模块被配置为基于在注入信号输入端接收到的注入信号，在LO输出端产生LO信号。 注入信号发生器模块具有多个LO输入和多个注入信号输出。 LO输入耦合到LO输出。 注入信号输出耦合到注入信号输入端。 注入信号发生器模块被配置为基于在LO输入上接收的LO信号并且基于接收的VCO信号，在喷射信号输出上产生喷射信号。