公开(公告)号：WO1993014464A1

公开(公告)日：1993-07-22

申请号：PCT/US1993000775

申请日：1993-01-15

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  ANTOSHENKOV, Gennady

IPC: G06F15/419

CPC classification number: G06F17/30327 ,  G06F17/30091 ,  Y10S707/99931

Abstract: A random sample is obtained from an inverted tree data structure by maintaining a cardinality estimate for each intermediate node in the tree, and selecting a leaf node at random by descending from the root node and performing an acceptance/rejection selection at each intermediate node weighted proportional to the cardinality estimates of the children and weighted inversely proportional to the cardinality estimate of the intermediate node. Even though the selection of an intermediate node is based upon only an estimate of the true cardinality of the intermediate node, the error in the estimate does not cause bias in the overall sampling method because any bias in the selection of the intermediate node is cncelled by an opposite bias in the selection of the child of the intermediate node. The cardinality estimates are maintained when a leaf is inserted or deleted from the data structure by checking whether the insertion or delection causes the cardinality estimate of a parent of the leaf node to differ from the actual cardinality by a predetermined error bound, and if so, the cardinality estimate of the parent is updated, and the checking and updating process is escalated up the tree. The error bound is adjustable for balancing rejection rate during sampling against I/O overhead of cardinality maintenance during database updates.

Abstract translation: 通过维持树中每个中间节点的基数估计，从反向树数据结构获得随机样本，并从根节点下降随机选择叶节点，并在每个中间节点进行接受/拒绝选择，加权比例 到儿童的基数估计，并加权与中间节点的基数估计成反比。 即使中间节点的选择仅基于中间节点的真实基数的估计，估计中的误差也不会导致整体采样方法中的偏差，因为中间节点的选择中的任何偏差由 在中间节点的孩子的选择中具有相反的偏差。 当从数据结构插入或删除叶子时，通过检查插入或选择是否导致叶节点的父节点的基数估计与预定误差界限的实际基数不同而保持基数估计，如果是， 更新父母的基数估计，检查和更新过程在树上升级。 错误限制是可调整的，以便在数据库更新期间对采样期间的排除率进行基数维护的I / O开销。

公开(公告)号：WO1993009499A1

公开(公告)日：1993-05-13

申请号：PCT/US1992009239

申请日：1992-10-27

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  ABADI, Martin ,  BURROWS, Michael ,  WOBBER, Edward, P.

IPC: G06F12/14

CPC classification number: G06F9/468 ,  Y10S707/99939

Abstract: A distributed computer system has a number of computers coupled thereto at distinct nodes and a naming service with a membership table that defines a list of assumptions concerning which principals in the system are stronger than other principals, and which roles adopted by principals are stronger than other roles. Each object in the system has an access control list (ACL) having a list of entries. Each entry is either a simple principal or a compound principal. The set of allowed compound principals is limited to a predefined set of allowed combinations of simple principals, roles, delegations and conjunctions in accordance with a defined hierarchical ordering of the conjunction, delegation and role portions of each compound principal. The assumptions in the membership table reduce the number of entries needed in an ACL by allowing an entry to state only the weakest principals and roles that are to be allowed access. The reference checking process, handled by a reference monitor found at each node of the distributed system, grants an access request if the requestor is stronger than any one of the entries in the access control list for the resource requested. Furthermore, one entry is stronger than another entry if for each of the conjuncts in the latter entry there is a stronger conjunct in the former. Additional rules used by the reference monitor during the reference checking process govern the processes of comparing conjuncts in a requestor principal with the conjuncts in an access control list entry and of using assumptions to compare the relative strengths of principals and roles.

Abstract translation: 分布式计算机系统具有多个与不同节点耦合的计算机，以及具有会员表的命名服务，该成员表定义了系统中哪些主体比其他主体更强的假设列表，以及由主体采用的角色比其他主体更强 角色。 系统中的每个对象都具有一个具有条目列表的访问控制列表（ACL）。 每个条目都是简单的主体或复合主体。 允许的复合主体的集合被限制为根据每个复合主体的连接，委派和角色部分的定义的分级顺序的简单主体，角色，委托和连接的允许的组合的预定义集合。 成员资格表中的假设通过允许条目仅指定允许访问的最弱主体和角色来减少ACL中所需的条目数。 如果请求者比所请求的资源的访问控制列表中的任何一个条目更强，则由在分布式系统的每个节点处发现的参考监视器处理的参考检查过程授予访问请求。 此外，如果对于前一个条目中的每个连词都有一个更强的连接，则一个条目比另一个条目更强。 引用检查过程中参考监视器使用的附加规则管理将请求方主体中的连接与访问控制列表条目中的连接进行比较的过程，以及使用假设来比较主体和角色的相对强度。

公开(公告)号：WO1993006657A1

公开(公告)日：1993-04-01

申请号：PCT/US1992008079

申请日：1992-09-23

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  IKNAIAN, Russell ,  WATSON, Richard, B., Jr. ,  COLLINS, Hansel, A.

IPC: H03K17/00

CPC classification number: G06F1/10 ,  G01R31/3016 ,  G01R31/31725 ,  G06F1/08 ,  H03K5/13 ,  H03K5/1508 ,  H03K17/005 ,  H04L7/0337

Abstract: An update synchronizer includes a two-stage synchronization unit for generating enable signals to select an output signal from among multiple input clock signals of a clock delay multiplexer. The enable signals originate from an asynchronous control signal having a phase different from that of the clock signals. A pre-synchronization logic stage transforms the asynchronous control signal into complementary synchronous control signals for use by the clock synchronization units; these synchronous control signals, in turn, are transformed into complementary selection enable signals having phases within the domains of the input clock signals. This ensures that transitions of the enable signals occur during the same clock period.

Abstract translation: 更新同步器包括两级同步单元，用于产生使能信号以从时钟延迟复用器的多个输入时钟信号中选择输出信号。 使能信号源自具有与时钟信号不同的相位的异步控制信号。 预同步逻辑级将异步控制信号转换为互补同步控制信号，供时钟同步单元使用; 这些同步控制信号又被转换成在输入时钟信号的域内具有相位的互补选择使能信号。 这确保使能信号的转换在相同的时钟周期内发生。

公开(公告)号：WO1993000651A1

公开(公告)日：1993-01-07

申请号：PCT/US1992005352

申请日：1992-06-25

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  SALTZO, Jeffrey, S. ,  CLIFFORD, William

IPC: G06F15/72

CPC classification number: G06T11/206

Abstract: The present invention pertains to a method for transforming non-geometric data into a volumetric representation. Non-geometric data is difficult to represent in three-dimensional space because there is typically no inherent spatial relationship between the data. The present invention transforms the data into a volumetric form and it is then displayed using known visualization techniques. The transformation to volumetric representation facilitates the viewer's perception of relationships between the data.

Abstract translation: 本发明涉及将非几何数据转换为体积表示的方法。 非几何数据难以在三维空间中表示，因为数据之间通常没有固有的空间关系。 本发明将数据转换为体积形式，然后使用已知的可视化技术来显示。 对体积表示的转换有助于观众对数据之间的关系的感知。

公开(公告)号：WO1992015940A1

公开(公告)日：1992-09-17

申请号：PCT/US1992001839

申请日：1992-03-04

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  MURPHY, Daniel, L.

IPC: G06F09/445

CPC classification number: G06F9/44521

Abstract: An improved method for linking images at program activation is provided by use of a symbol vector in a sharable code image. The symbol vector is automatically constructed which the linker and operating system use to effect fast lookup of symbol values at program activation, thus providing flexibility similar to that of link-time binding. For each sharable image being constructed, the programmer provides a list of symbols which are to be made visible outside of the image. These symbols may be procedure names, data cells, absolute values, or any other valid use of a symbolic value. The order of this list must remain fixed from one image build to the next. From this list, the 'symbol vector' is constructed (as by the linker) of the value of each of the identified symbols, and the symbol vector is associated with the sharable image. A symbol table is also associated with the sharable image, where each symbol has the value of its index in the symbol vector. When resolving references to other images, the linker does a symbolic lookup in the symbol table of the target image and obtains the index into t the target symbol vector. That index is bound into the calling image. Then, at program activation, the image activator uses the index bound into a calling image to obtain the current value of the symbol in the target image.

公开(公告)号：WO1992015936A1

公开(公告)日：1992-09-17

申请号：PCT/US1992001771

申请日：1992-03-03

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  MURPHY, Daniel, L.

IPC: G06F09/40

CPC classification number: G06F9/541 ,  G06F9/4484

Abstract: A jacketing system automatically interface dissimilar program units during program execution on a computer system. Means are provided for detecting a call for execution of a second program unit having a second call standard from a first program unit having a first call standard during execution of the first program unit on the computer system. A procedure descriptor is used in the code for the first program unit and it includes a signature that defines the call standard for each incoming call to the first program unit. A bound procedure descriptor is also used in the code for each outgoing call from the first program unit and it includes a signature that defines the call standard for the target program unit. Jacketing routines are driven by the descriptors in jacketing calls between the two program units.

Abstract translation: 护套系统在计算机系统的程序执行期间自动接口不同的程序单元。 提供了用于在计算机系统上执行第一程序单元期间从具有第一呼叫标准的第一程序单元检测执行具有第二呼叫标准的第二程序单元的呼叫的装置。 在第一程序单元的代码中使用过程描述符，并且其包括为每个到第一程序单元的来话呼叫定义呼叫标准的签名。 绑定过程描述符也用于来自第一程序单元的每个去话呼叫的代码，并且它包括定义目标程序单元的呼叫标准的签名。 夹克程序由两个程序单元之间的外挂呼叫的描述符驱动。

公开(公告)号：WO1992014202A1

公开(公告)日：1992-08-20

申请号：PCT/US1992000882

申请日：1992-02-03

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  ULRICH, Ernst, G. ,  LENTZ, Karen, P. ,  GUSTIN, Michael, M.

IPC: G06F11/00

CPC classification number: G06F11/3608 ,  G06F11/3672

Abstract: A simulation method allowing an experimenter to test and debug computer programs concurrently. The method utilizes the generation of signatures to observe interactions of various subprogram paths with a reference case.

Abstract translation: 一种允许实验者同时测试和调试计算机程序的模拟方法。 该方法利用生成签名来观察各种子程序路径与参考案例的交互。

公开(公告)号：WO1992014201A1

公开(公告)日：1992-08-20

申请号：PCT/US1992000881

申请日：1992-02-03

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  ULRICH, Ernst, G. ,  LENTZ, Karen, Panetta

IPC: G06F15/60

CPC classification number: G06F17/5009 ,  G06F11/3604

Abstract: A simulation method allowing an experimenter to model a real-word situation in order to learn something about it. The method permits interaction of concurrent experiments through interaction between different variables during a single simulation run on a computer having at least one central processing unit.

Abstract translation: 一种模拟方法，允许实验者对真实情况进行建模，以便了解有关它的内容。 该方法允许通过在具有至少一个中央处理单元的计算机上的单个模拟运行期间通过不同变量之间的交互来进行并行实验的交互。

公开(公告)号：WO1992005486A1

公开(公告)日：1992-04-02

申请号：PCT/US1991006676

申请日：1991-09-13

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  GAGLIARDO, Michael, A. ,  TESSARI, James, E. ,  COLLINS, Hansel, A. ,  LYNCH, John ,  CHINNASWAMY, Kumar

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: For the detection of errors in DRAM-control signals transmitted across an interconnect between system modules, a comparison of the parity of the control signals as transmitted and as received is performed at the transmitter module. The transmitter module is provided with a parity generator for determining the parity of the control signals being transmitted. The receiver module is provided with a similar parity generator for determining the parity of the control signals as received from the interconnect. The receiver module generates a parity signal indicating the parity determined by the parity generator in the receiver module, and transmits the parity signal over the interconnect to the transmitter module. At the transmitter module, the parity indicated by the parity signal is compared with the parity determined by the parity generator in the transmitter module for generating an error signal when the parity indicated by the parity signal is unequal to the parity determined by the parity generator in the transmitter module. Preferably one of the DRAM-control signals is used as a time reference for determining the point at which the parity signal from the receiver module is compared to the parity determined for previously transmitted control signals. A delay of a predetermined period of time is provided between the time that the control signals are transmitted from the transmitter module and the point at which the comparison of parity signals is performed: this predefined delay is based upon the time required for signals to traverse, in both directions, the path through the interconnection between the transmitter module and the receiver module, as well as the clock skews inherent in the modules.

Abstract translation: 为了检测通过系统模块之间的互连发送的DRAM控制信号中的错误，在发射机模块处执行发送和接收的控制信号的奇偶校验的比较。 发射机模块设置有用于确定被发送的控制信号的奇偶校验的奇偶校验发生器。 接收器模块设置有类似的奇偶校验发生器，用于确定从互连接收的控制信号的奇偶性。 接收器模块产生指示由接收机模块中的奇偶校验发生器确定的奇偶校验的奇偶校验信号，并且通过互连将奇偶校验信号发送到发射机模块。 在发射机模块处，将由奇偶校验信号指示的奇偶校验与由发射机模块中的奇偶校验发生器确定的奇偶校验进行比较，以便在奇偶校验信号所指示的奇偶校验不等于由奇偶校验发生器确定的奇偶校验位时产生误差信号 发射机模块。 优选地，DRAM控制信号中的一个用作用于确定来自接收机模块的奇偶校验信号与为先前发送的控制信号确定的奇偶校验相比较的点的时间基准。 在从发射机模块发送控制信号的时间与执行奇偶校验信号的比较的点之间提供预定时间段的延迟：该预定义延迟基于信号穿越所需的时间， 在两个方向上，通过发射器模块和接收器模块之间的互连的路径，以及模块中固有的时钟偏移。

公开(公告)号：WO1990009630A1

公开(公告)日：1990-08-23

申请号：PCT/US1990000804

申请日：1990-02-16

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  ADILETTA, Matthew, J.

IPC: G06F07/52

CPC classification number: G06F7/535 ,  G06F7/5375

Abstract: An optimized division circuit and a method of implementing the circuit includes the steps of determining a Z-Z plot relationship which represents a relationship between a first divisor ratio proportional to a range of previously determined remainder values divided by the divisor and a second divisor ratio equal to a range of succeeding remainder values divided by the divisor. A complete look-up table is automatically built from the Z-Z plot relationship which includes, for each different valid combination of divisor and next remainder values, either a corresponding quotient digit or a DON'T CARE indicator. A state value, used in the logical implementation of the circuit, is then assigned to each different quotient digit. The circuit includes a divisor multiple formation circuit, a quotient determining circuit and a quotient assimilation circuit. The divisor multiple formation circuit includes a divisor multiple multiplexer. The quotient determining circuit includes a next partial remainder determining circuit and a next quotient digit selection circuit. The quotient assimilation circuit subtracts negative values of quotient digits from positive values to determine a final quotient value.