公开(公告)号：WO1994000937A1

公开(公告)日：1994-01-06

申请号：PCT/US1993005918

申请日：1993-06-21

Applicant: DIGITAL EQUIPMENT CORPORATION ,  DIGITAL EQUIPMENT INTERNATIONAL LTD.

Inventor： DIGITAL EQUIPMENT CORPORATION ,  DIGITAL EQUIPMENT INTERNATIONAL LTD. ,  HIGGINSON, Peter, Leslie ,  BERENT, Anthony, Neil

IPC: H04L01/00

CPC classification number: H04L1/0061 ,  H04L1/0065 ,  H04L1/0072 ,  H04L1/0083

Abstract: A packet is originated in a unit (10) as a data field DATA (11) plus a CRC (cyclic redundancy check) check field CRC (12) by a CRC circuit (13). This packet has a header HDR (with a routing information field RIF) added to it in a unit (20), converting it into a message for transmission through a message network. A check correction field CCF is computed by unit (23) in unit (20), by looking up precomputed check subfields stored with the routing subfields (the routing information field being constructed by selecting from the stored subfields), such that the CRC field is a valid CRC check field for the complete message. At the destination, unit (30) can be the final user unit, checking the entire message and extracting the data field DATA therefrom; the DATA field does not need to be checked, as the CRC field acts as a check both for the data field DATA alone and the entire message. (Alternatively, the message can be checked by a final switching unit (30) using a standard CRC check circuit (32) (and similarly at intermediate units 30', 30'') and the original packet can be checked by another standard CRC check circuit (42) in the final user unit (40)).

Abstract translation: 分组由CRC电路（13）作为数据字段DATA（11）加上CRC（循环冗余校验）校验字段CRC（12）在单元（10）中发起。 该分组具有在单元（20）中添加到其中的报头HDR（具有路由信息字段RIF），将其转换成用于通过消息网络传输的消息。 通过查找存储有路由子字段的预计算校验子字段（通过从存储的子字段中选择构建的路由信息​​字段），校验校正字段CCF由单元（20）中的单元（23）计算，使得CRC字段为 用于完整消息的有效CRC校验字段。 在目的地，单元（30）可以是最终用户单元，检查整个消息并从中提取数据字段DATA; DATA字段不需要检查，因为CRC字段用作单独的数据字段DATA和整个消息的检查。 （或者，可以使用标准CRC校验电路（32）（并且类似地在中间单元30'，30“）由最终切换单元（30）检查消息，并且可以通过另一标准CRC校验来检查原始分组 在最终用户单元（40）中的电路（42））。

公开(公告)号：WO1993026089A1

公开(公告)日：1993-12-23

申请号：PCT/US1993005188

申请日：1993-06-01

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  SIMONELLI, James, M. ,  ARBANAS, Zeljko

IPC: H03F15/00

CPC classification number: H03F15/00

Abstract: A galvanically isolated error amplifier using Hall effect principles for application in control circuitry. Input currents to be compared are conducted through respective windings around a gapped ferrite toroidal core. A standard Hall effect magnetic field sensor/amplifier positioned in the gap provides a voltage signal proportional to the difference in the current inputs.

Abstract translation: 使用霍尔效应原理的电流隔离误差放大器用于控制电路中的应用。 要比较的输入电流通过围绕有间隙的铁氧体环形磁芯的相应绕组进行。 定位在间隙中的标准霍尔效应磁场传感器/放大器提供与电流输入的差异成比例的电压信号。

公开(公告)号：WO1993026087A1

公开(公告)日：1993-12-23

申请号：PCT/US1993004793

申请日：1993-05-21

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  DALY, James, A.

IPC: H03F03/08

CPC classification number: H03F3/38 ,  H03F1/347

Abstract: An isolation amplifier employs feedback to accurately amplify an input signal (Sin) while maintaining electrical isolation between the input and output signals (Sout). The isolation amplifier consists of an amplitude modulator, an isolation transformer (101), having a pair of matched secondary windings, a peak-detector output circuit, and a matching peak-detector feedback circuit. The isolation transformer (101) couples an amplitude-modulated signal to both peak detector circuits while maintaining electrical isolation. The output from the feedback circuit is fed back to the amplitude modulator, so that the amplitude-modulated signal represents the difference between the input to the amplifier and the feedback signal.

公开(公告)号：WO1993022837A1

公开(公告)日：1993-11-11

申请号：PCT/US1993003800

申请日：1993-04-21

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  MASKAS, Barry, A ,  METZGER, Jeffery, A. ,  HARRIS, George, J.

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/00384

Abstract: A circuit for converting the logic voltage levels from those of a first device to those of a second device. This conversion is accomplished while substantially isolating the second device from the effects of the first device that could influence the outputs of the second device that represent the converted logic level voltages.

Abstract translation: 用于将逻辑电压电平从第一器件的电压电平转换为第二器件的逻辑电压电平的电路。 实现这一转换，同时基本上将第二装置与第一装置的影响相分离，这可能影响表示转换的逻辑电平电压的第二装置的输出。

公开(公告)号：WO1993018589A1

公开(公告)日：1993-09-16

申请号：PCT/US1993002658

申请日：1993-03-12

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  WENG, Lih-Jyh

IPC: H03M13/00

CPC classification number: G06F11/1044 ,  G06F11/10 ,  G06F11/187 ,  G06F2201/81 ,  G11C29/74 ,  H03M13/43 ,  H04L1/08

Abstract: A method of data recovery in systems employing error-correction coding techniques is described. The technique may be used, for example, in conjunction with a data storage device (12). Several trials of accessing the ECC-protected data are performed. The data from each trial (20) is decoded, and is also saved. If none of the trials results in the successful decoding of the data, then a reconstruction function is employed to create a reconstructed version of the data (22) from the sequence of data created by the trials. One method of reconstruction involves majority voting on a symbol-by-symbol (21) basis. The reconstructed data created that way is then decoded in the same fashion as for each trial. A more powerful reconstruction function employs a threshold to determine whether each voted-on-symbol is sufficiently ''reliable''. If not, it is marked as an erasure. The reconstructed data created by this reconstruction function is decoded according to an error-and-erasure algorithm, which increases the error-correcting power of the ECC.

Abstract translation: 描述了采用纠错编码技术的系统中的数据恢复方法。 该技术可以例如与数据存储设备（12）结合使用。 执行访问ECC保护数据的几个试验。 来自每个试验（20）的数据被解码，并且也被保存。 如果没有一个试验导致数据的成功解码，则采用重建函数来从试验创建的数据序列创建数据（22）的重建版本。 一种重建方法涉及按符号（21）的多数投票。 然后以与每个试验相同的方式对创建的重建数据进行解码。 更强大的重建功能采用阈值来确定每个投票符号是否足够“可靠”。 如果没有，它被标记为擦除。 根据错误和擦除算法对由该重构功能创建的重建数据进行解码，这增加了ECC的纠错能力。

公开(公告)号：WO1993012482A1

公开(公告)日：1993-06-24

申请号：PCT/US1991009205

申请日：1991-12-09

Applicant: DIGITAL EQUIPMENT CORPORATION ,  KIRK, Steven, A. ,  BARABASH, William ,  YERAZUNIS, William, S.

Inventor： DIGITAL EQUIPMENT CORPORATION

IPC: G06F09/44

CPC classification number: G06N5/047

Abstract: A pattern match method is the primary component of any rule-based inference engine or database search method. Equivalence class projection is used in a discrimination match network, such that only equivalence class tokens (and not working memory objects) are propagated down the network, then only the first object which is a member of any specific equivalence class will cause an actual propagation down through the net. Subsequent changes which are either the creation of new objects which are members of a known equivalence class or the removal of any object but the last member of that equivalence class can totally avoid propagation downward in that section of the discrimination network.

Abstract translation: 模式匹配方法是任何基于规则的推理引擎或数据库搜索方法的主要组成部分。 等价类投影用于鉴别匹配网络，使得只有等同类令牌（而不是工作的内存对象）才能从网络传播，则只有作为任何特定等价类成员的​​第一个对象将导致实际传播下降 通过网。 作为已知等效类的成员的新对象的创建或者该等价类的最后一个成员的删除，可以完全避免在该辨别网络的该部分向下传播。

公开(公告)号：WO1993006497A1

公开(公告)日：1993-04-01

申请号：PCT/US1992008087

申请日：1992-09-23

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  IKNAIAN, Russell ,  WATSON, Richard, B., Jr. ,  COLLINS, Hansel, A.

IPC: G01R31/28

CPC classification number: G06F1/10 ,  G01R31/3016 ,  G01R31/31725 ,  G06F1/08 ,  H03K5/13 ,  H03K5/1508 ,  H03K17/005 ,  H04L7/0337

Abstract: A test register coupled to an absolute delay regulator circuit of a clock repeater chip enables complete functional testing of a clock delay path of the regulator. The test register is connected to a measurement latch of the clock path in a "logical OR" configuration with respect to a measurement delay line and is enabled during a test mode by control logic of the repeater chip. Operationally, a sequence of logic "0" bits are forced in the measurement delay line during test mode. A state machine clears the measurement latch, and then loads a test pattern into the test register. As each bit of the register is set, a corresponding bit in the measurement latch is also set to simulate a measurement cycle; the results of the "measurement" are stored in the measurement latch. Once the test pattern is loaded, the repeater chip is placed into a measurement test mode. Execution of a measurement test cycle then propagates the test pattern throughout the clock delay path of the regulator. An output clock signal is sampled and if determined present, indicates that the clock path column under test is functional. Each column of the clock path is then tested separately in sequence.

Abstract translation: 耦合到时钟中继器芯片的绝对延迟调节器电路的测试寄存器使得能够对调节器的时钟延迟路径进行完整的功能测试。 测试寄存器以相对于测量延迟线的“逻辑OR”配置连接到时钟路径的测量锁存器，并且在测试模式期间通过中继器芯片的控制逻辑使能该测试寄存器。 在测试模式下，在测量延迟线中强制执行一系列逻辑“0”位。 状态机清除测量锁存器，然后将测试模式加载到测试寄存器中。 当寄存器的每个位被置位时，测量锁存器中的相应位也被设置为模拟测量周期; “测量”的结果存储在测量锁存器中。 一旦加载了测试图案，就将中继器芯片置于测量测试模式。 测量测试周期的执行然后在调节器的整个时钟延迟路径中传播测试图案。 输出时钟信号被采样，并且如果确定存在，则指示正在测试的时钟路径列是有效的。 时钟路径的每一列然后依次单独测试。

公开(公告)号：WO1993004462A1

公开(公告)日：1993-03-04

申请号：PCT/US1992007055

申请日：1992-08-21

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  MEINERTH, Kim ,  BOUCHARD, Joseph ,  CASE, Colyn ,  CROUSE, Robert ,  FANNING, Blaise ,  FIELDING, Kevin ,  FRANKLIN, Chris ,  GAMACHE, Rodney ,  IRWIN, John ,  KIRK, John ,  KRISHNASWAMI, Srinivasan ,  LORD, George ,  MASUCCI, Agnes, M. ,  MOEZZI, Ali ,  PAYSON, Christopher, J. ,  SCOTT, George

IPC: G09G05/40

CPC classification number: G09G5/393 ,  G06F9/3879 ,  G06F12/0831 ,  G06F12/1027 ,  G09G5/06 ,  G09G5/08 ,  G09G5/363 ,  G09G2310/04 ,  G09G2360/121 ,  G09G2360/123 ,  G09G2360/126

Abstract: A low cost, high performance computer graphics system. A graphics processor, capable of making memory requests is connected to a memory control unit, which controls a memory bus. Both main memory and a frame buffer memory are attached to the memory bus, thereby giving the graphics processor the capability of writing to either main memory or to the frame buffer memory. The disclosure further describes a computer graphics system, having a duplicate cache tag store accessible by the graphics system without generating traffic on the system bus; having a FIFO command buffer in main memory for temporary storage of graphics commands; having a residue buffer for the temporary storage of memory transmissions not immediately usable by the graphics processor; having a "short circuit" feature for routing graphics commands to the command processor in the minimum number of steps; having a cursor control system capable of storing cursor pattern information in, and retrieving cursor pattern information from, main memory; having a cursor bus that is reconfigurable to carry information other than cursor information; and having a frame buffer module that contains no timing or cursor control circuitry.

Abstract translation: 低成本，高性能的计算机图形系统。 能够进行存储器请求的图形处理器连接到控制存储器总线的存储器控​​制单元。 主存储器和帧缓冲存储器都附加到存储器总线，从而给图形处理器写入主存储器或帧缓冲存储器的能力。 本公开还描述了一种计算机图形系统，其具有由图形系统可访问的重复高速缓存标签存储器，而不在系统总线上产生业务; 在主存储器中具有用于临时存储图形命令的FIFO命令缓冲器; 具有用于临时存储图形处理器不能立即使用的存储器传输的残留缓冲器; 具有用于以最小数量的步骤将图形命令路由到命令处理器的“短路”特征; 具有能够将光标图案信息存储在主存储器中并从主存储器检索光标图案信息的光标控制系统; 具有可重配置以携带除光标信息之外的信息的光标总线; 并具有不包含定时或光标控制电路的帧缓冲器模块。

公开(公告)号：WO1993004457A2

公开(公告)日：1993-03-04

申请号：PCT/US1992007056

申请日：1992-08-21

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  CASE, Colyn ,  FANNING, Blaise ,  IRWIN, John ,  MASUCCI, Agnes, M. ,  MEINERTH, Kim ,  MOEZZI, Ali

IPC: G09G01/16

CPC classification number: G09G5/14 ,  G09G5/024 ,  G09G5/346 ,  G09G5/363 ,  G09G5/393 ,  G09G2310/04 ,  G09G2360/122

Abstract: In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. A separate translator provides conversion from generated virtual addresses to physical addresses. The address generator formulates addresses as a function of distance from the origin of desired destination area in destination memory to the requested position in the destination area. A plurality of drawing graphics commands specify different raster drawing operations. A plurality of context graphics commands is used to define a desired context in which drawing graphics commands operate. The defined context includes destination location for resulting data, type and plane depth of graphics operations, foreground and/or background color of resulting data. Different parts of the context are changeable/redefinable independently of the other parts. The graphics commands have a format of multiple fields. Different fields specify different parameters. For each graphics command, the fields are arranged in order of common use of the corresponding parameter such that fields of less commonly used parameters are at an omittable end of the format. Thus, length of each graphics command varies as a function of parameters specified in the graphics command. A desired set of raster drawing commands delimited by a beginning indicator and an end indicator form a drawing unit. For clip list processing, a drawing unit is stored as a single occurrence in the system command buffer but functionally serves as a processing loop. Processing alternates between the drawing unit held in the command buffer and a clip list that specifies desired clip rectangles, the drawing unit being repeated for each clip rectangle.

Abstract translation: 在计算机图形系统中，地址生成器使用公共命令集处理物理和虚拟地址。 单独的翻译器提供从生成的虚拟地址到物理地址的转换。 地址生成器根据从目的地存储器中的期望目的地区域的原点到目的地区域中的请求位置的距离来形成地址。 多个绘图图形命令指定不同的光栅绘图操作。 使用多个上下文图形命令来定义绘图图形命令操作的所需上下文。 定义的上下文包括结果数据的目标位置，图形操作的类型和平面深度，结果数据的前景和/或背景颜色。 上下文的不同部分可以独立于其他部分进行变化/重新定义。 图形命令具有多个字段的格式。 不同的字段指定不同的参数。 对于每个图形命令，这些字段按照相应参数的共同使用的顺序排列，使得较不常用的参数的字段处于格式的可忽略的结尾。 因此，每个图形命令的长度根据图形命令中指定的参数的函数而变化。 由开始指示符和结束指示符分隔的所需的一组光栅绘图命令形成绘图单元。 对于剪辑列表处理，绘图单元作为一次出现存储在系统命令缓冲器中，但功能上用作处理循环。 处理在保存在命令缓冲器中的绘图单元和指定所需的剪辑矩形的剪辑列表之间交替，对每个剪辑矩形重复绘图单元。

公开(公告)号：WO1993003563A1

公开(公告)日：1993-02-18

申请号：PCT/US1992006264

申请日：1992-07-28

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  YANG, Henry, Sho-Che ,  RAMAKRISHNAN, Kadangode, K.

IPC: H04L12/42

CPC classification number: H04L12/42 ,  H04L12/433

Abstract: A purging station selected for removal of no-owner frames in a token ring network, and a corresponding method for its operation. The purging station initiates a purge cycle only if the network is no "idle" and, optionally, only if the network is not "near fully loaded", these terms being defined in relation to a token cycle. Therefore, no unnecessary purge marker frames are transmitted onto the network when it is idle or near fully loaded. Once purging is initiated, the purging station transmits at least one purge marker frame onto the ring network, and strips data received from the ring until a purge termination flag is set, upon detection of a received purge marker frame, a received token, or detection of a ring re-initialization procedure.

Abstract translation: 选择用于去除令牌环网络中不拥有帧的清除站，以及用于其操作的相应方法。 净化站只有在网络不是“空闲”的情况下启动清除循环，并且可选地，只有当网络不是“接近完全加载”时，这些术语就是相对于令牌周期来定义的。 因此，当空闲或接近满载时，不会将不必要的清除标记帧传输到网络上。 一旦清除开始，清除站将至少一个清除标记框架发送到环网上，并且在检测到接收到的清除标记帧，接收的标记或检测时，剥离从环接收的数据，直到设置清除终止标志 的环重新初始化程序。