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公开(公告)号：WO2015119668A1
公开(公告)日：2015-08-13
申请号：PCT/US2014/058281
申请日：2014-09-30
Inventor： HEZAR, Rahmi , DING, Lei , HAROUN, Baher
CPC classification number: H04L27/3411 , H03F1/02 , H03F1/0294 , H03F3/19 , H03F3/2175 , H03F3/245 , H03F2200/331 , H03F2200/336 , H03F2200/451 , H04B1/02 , H04B14/062 , H04L27/2053
Abstract: In described examples, at least one tone is generated (114). An output signal is generated (106) in response to an input signal (104) and the at least one tone. The output signal is modulated (120). The input signal (104) and the at least one tone are represented in the modulated output signal. The at least one tone is outside a bandwidth of the input signal (104) as represented in the modulated output signal. The modulated output signal is amplified (122). The at least one tone in the amplified signal is attenuated (124) after the amplifying.
Abstract translation: 在所描述的示例中，生成至少一个音调（114）。 响应于输入信号（104）和至少一个音调产生（106）输出信号。 输出信号被调制（120）。 在调制输出信号中表示输入信号（104）和至少一个音调。 至少一个音调在输入信号（104）的带宽之外，如在调制输出信号中所表示的。 调制输出信号被放大（122）。 在放大后，放大信号中的至少一个音调被衰减（124）。
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公开(公告)号：WO2015077482A1
公开(公告)日：2015-05-28
申请号：PCT/US2014/066670
申请日：2014-11-20
Inventor： SHENG, Zhongyan
CPC classification number: H04N9/3173 , G02B17/04 , G02B19/0023 , G02B19/0066 , G03B21/008 , G03B21/2013 , G03B21/2033 , G03B21/2066 , G03B21/28 , H04N9/3102 , H04N9/3176
Abstract: In described examples, apparatus (130) for light projection includes at least one illumination device (131). A cover prism (135) includes a curved surface (141) positioned to receive illumination light rays (153) and a total internal reflection surface positioned to internally reflect the light rays towards an asymmetric reflector surface (143) positioned opposite the total internal reflection surface. The asymmetric reflector surface (143) is configured to reflect the received light rays out of the cover prism (135) at an emitter side of the cover prism. A spatial light modulator (139) modulates the illumination light rays with image data to form image light rays. A reverse total internal reflection (RTIR) (133) prism is positioned between the spatial light modulator (139) and the emitter side of the cover prism (135). A total internal reflection surface is configured to totally internally reflect the image light rays out of the RTIR prism (133) into a light projection device (145).
Abstract translation: 在所述实施例中，用于光投射的装置（130）包括至少一个照明装置（131）。 盖棱镜（135）包括定位成接收照明光线（153）的弯曲表面（141）和设置成将光线内部反射到与全内反射表面相对定位的不对称反射器表面（143）的全内反射表面 。 不对称反射器表面（143）被配置为在盖棱镜的发射极侧将接收的光线反射出盖棱镜（135）。 空间光调制器（139）利用图像数据调制照明光线以形成图像光线。 反向全内反射（RTIR）（133）棱镜位于空间光调制器（139）和盖棱镜（135）的发射极侧之间。 全内反射面被配置成将从RTIR棱镜133的图像光线全部内反射成光投射装置145。
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公开(公告)号：WO2015069388A1
公开(公告)日：2015-05-14
申请号：PCT/US2014/058170
申请日：2014-09-30
Inventor： JAIN, Karan, Singh , MERKIN, Timothy, Bryan , CURTIS, Susan
IPC: G05F1/575
Abstract: In described examples of limiting current in a low dropout ("LDO") linear voltage regulator (300), a pass element (330) generates an output voltage (VOUT) that is less than an input voltage. The pass element (330) may be enabled by an error amplifier (3 10) that compares a feedback signal (VFB) from an output (335) of the pass element (330) with a voltage reference (VREF). Also, the pass element (330) may be enabled by a current limiting circuit (353, 354, 355) that bypasses the error amplifier (3 10) to limit current generated at the output (335) of the pass element (330).
Abstract translation: 在限制低压差（“LDO”）线性稳压器（300）中的电流的示例中，通过元件（330）产生小于输入电压的输出电压（VOUT）。 传递元件（330）可以由将通过元件（330）的输出（335）的反馈信号（VFB）与电压基准（VREF）进行比较的误差放大器（310）来使能。 此外，通过元件（330）可以通过绕过误差放大器（310）限制在通过元件（330）的输出（335）处产生的电流的限流电路（353,354,355）使能。
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公开(公告)号：WO2015048366A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/057579
申请日：2014-09-26
Inventor： GAHOI, Anshul , SANTHANAGOPAL, Raghavendra , BABU, Pradeep, Kumar
IPC: G06F11/263
CPC classification number: G06F11/27 , G01R13/28 , G01R31/3177 , G06F9/44 , G06F11/273 , G06F17/5027 , G06F17/5054
Abstract: In described examples, a test connector is arranged to communicatively couple a design under test (460) to a test fixture. A programmable logic interface (450) is communicatively coupled to the test connector and is arranged to receive a downloadable test bench (454). The downloadable test bench (454) is arranged to apply test vectors from a first set of test vectors (444) to a first test control bus (458). A multiplexer (462) is arranged to selectively couple one of the first test control bus (458) and a second test control bus (464) to a shared test bus (466) that is coupled to the test connector. The second test control bus (464) is arranged to apply test vectors from a second set of test vectors.
Abstract translation: 在所描述的示例中，测试连接器布置成将被测试设计（460）通信地耦合到测试夹具。 可编程逻辑接口（450）通信地耦合到测试连接器并被布置成接收可下载的测试台（454）。 可下载测试台（454）被布置成将来自第一组测试向量（444）的测试向量应用于第一测试控制总线（458）。 复用器（462）布置成选择性地将第一测试控制总线（458）和第二测试控制总线（464）中的一个耦合到耦合到测试连接器的共享测试总线（466）。 第二测试控制总线（464）被布置成从第二组测试向量应用测试向量。
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公开(公告)号：WO2015010089A1
公开(公告)日：2015-01-22
申请号：PCT/US2014/047298
申请日：2014-07-18
Inventor： BI, Xiaochuan , KRAKOWSKI, Tracey, L. , WEISER, Doug
IPC: H01L21/329 , H01L29/864
CPC classification number: H01L29/864 , H01L27/0635 , H01L29/0649 , H01L29/161 , H01L29/165 , H01L29/66159
Abstract: In described examples, a vertical IMPATT diode (300) is fabricated in a standard planar analog process flow.
Abstract translation: 在所描述的示例中，在标准平面模拟处理流程中制造垂直IMPATT二极管（300）。
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Patent Agency Ranking
公开(公告)号：WO2014190344A1
公开(公告)日：2014-11-27
申请号：PCT/US2014/039552
申请日：2014-05-27
Inventor： JOSHI, Alok, Prakash , RAJENDRAN, Gireesh
Abstract: In described examples, a coupling circuit (310) includes a primary winding (312), a first secondary winding (320a) and a second secondary winding (320b). The first secondary winding (320a) and the second secondary winding (320b) are inductively associated with the primary winding (312). The coupling circuit (310) is configured to provide a signal at output terminals (322, 324, 326, 328) of the first secondary winding (320a) and the second secondary winding (320b) in response to an input signal (314, 316) received at the primary winding (312). A first power amplifier circuit (340a) is coupled to output terminals (322, 324) of the first secondary winding (320a), and a second power amplifier circuit (340b) is coupled to output terminals (326, 328) of the second secondary winding (320b). Each power amplifier circuit (340a, 340b) is configured to be enabled or disabled based on a bias voltage (Vbiasl, Vbias2) applied at a corresponding secondary winding (320a, 320b).
Abstract translation: 在所述示例中，耦合电路（310）包括初级绕组（312），第一次级绕组（320a）和第二次级绕组（320b）。 第一次级绕组（320a）和第二次级绕组（320b）与初级绕组（312）感应地相关联。 耦合电路（310）被配置为响应于输入信号（314,316）而在第一次级绕组（320a）和第二次级绕组（320b）的输出端子（322,324,326,328）处提供信号 ）接收在初级绕组（312）。 第一功率放大器电路（340a）耦合到第一次级绕组（320a）的输出端子（322,324），并且第二功率放大器电路（340b）耦合到第二次级绕组的输出端子（326,328） 绕组（320b）。 每个功率放大器电路（340a，340b）被配置为基于施加在对应的次级绕组（320a，320b）上的偏置电压（Vbias1，Vbias2）而被使能或禁用。
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公开(公告)号：WO2020146624A1
公开(公告)日：2020-07-16
申请号：PCT/US2020/012922
申请日：2020-01-09
Inventor： RANMUTHU, Indumini
IPC: H01L27/105 , H03K17/04
Abstract: An example apparatus includes a first power field-effect transistor (FET) (204) having a first source (306), and a second power FET (206) having a second source (308). The first and second power FETs (204, 206) share a common drain (402). The first and second sources (306, 308) are positioned on a first side of a substrate (406), and the common drain (402) is positioned on a second side of the substrate (406) opposite the first side. The example apparatus includes a current sensing FET positioned between first and second portions of the first source (306). The current sensing FET senses a current passing through the first and second power FETs (204, 206).
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公开(公告)号：WO2020139778A1
公开(公告)日：2020-07-02
申请号：PCT/US2019/068037
申请日：2019-12-20
Inventor： DING, Lei , RAMASWAMY, Srinath , DABAK, Anand
IPC: G01S15/52
Abstract: An ultrasound detect circuit (210) includes a decimator (314) that decimates a transmit signal to be transmitted through an ultrasonic transducer. The transmit signal is decimated to generate first and second template signals. The decimator (314) uses a different decimation ratio to generate the first template signal than the second template signal. The circuit (210) also includes a first correlator (306) to correlate a signal derived from the ultrasonic transducer with the first template signal, a second correlator (308) to correlate the signal derived from the ultrasonic transducer with the second template signal, and a Doppler shift determination circuit (325) to determine a Doppler frequency shift based on an output from the first correlator (306) and an output from the second correlator (308).
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公开(公告)号：WO2020072475A1
公开(公告)日：2020-04-09
申请号：PCT/US2019/054037
申请日：2019-10-01
Inventor： YAN, Yi , NGUYEN, Luu, Thanh , PRABHU, Ashok , PODDAR, Anindya
Abstract: In examples, a device includes: magnetic layers (202, 206, 214, 222) including magnetic ink residue; and metallic layers (203, 204, 210, 212, 218, 220, 226, 228) including metallic ink residue and coupled to the magnetic layers (202, 206, 214, 222). The metallic layers (203, 204, 210, 212, 218, 220, 226, 228) are coupled to each other to form a coil.
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公开(公告)号：WO2019213654A1
公开(公告)日：2019-11-07
申请号：PCT/US2019/030892
申请日：2019-05-06
Inventor： YAO, Henry , PAREKH, Sinjeet, Dhanvantray
Abstract: A time-to-digital converter circuit (100) includes a logic gate (130) configured to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate (130) is configured to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit (133) is coupled to the logic gate (130) and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit (150, 158) counts pulses of the synchronization output signal.
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