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公开(公告)号：WO9946886A3
公开(公告)日：2000-03-02
申请号：PCT/US9904437
申请日：1999-02-26
Applicant: EPIGRAM INC
Inventor： OJARD ERIC , TRACHEWSKY JASON , HOLLOWAY JOHN T , FRANK EDWARD H , PETERSON KEVIN H
IPC: H04L13/08 , H04L1/00 , H04L7/027 , H04L7/04 , H04L7/10 , H04L12/413 , H04L25/03 , H04L27/26 , H04L29/06 , H04L29/10 , G06F13/12 , H04L25/497 , H04L27/38
CPC classification number: H04L12/40032 , H04L1/0054 , H04L1/0065 , H04L7/027 , H04L7/041 , H04L7/10 , H04L12/40013 , H04L12/413 , H04L25/03057 , H04L27/2647
Abstract: A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to host computer formatted data separately from receiving the data packet. The network interface receives the data packet, converts the analog signal to a digitized signal, and stores the resulting sample packet in a storage queue. An off-line processor, which may be the host computer itself, performs the signal processing required to interpret the sample packet. In transmission, the off-line process converts host-formatted data to a digitized version of a transmission data packet and stores that in a transmission queue. A transmitter converts the transmission data packet format and transmits the data to the shared medium.
Abstract translation: 提出了一种从共享介质接收分组数据并实现将数据分组转换为主计算机格式化数据所需的信号处理的网络接口，与接收数据分组不同。 网络接口接收数据包，将模拟信号转换为数字信号，并将生成的样本包存储在存储队列中。 可能是主计算机本身的离线处理器执行解释样本分组所需的信号处理。 在传输中，离线过程将主机格式的数据转换为传输数据分组的数字化版本，并将其存储在传输队列中。 发射机转换传输数据包格式并将数据发送到共享介质。
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42.发明申请METHOD AND APPARATUS FOR CLOCK TIMING RECOVERY IN chi DSL, PARTICULARLY VDSL MODEMS 审中-公开用于时钟恢复的方法和装置，特别是VDSL模式
公开(公告)号：WO99048219A1
公开(公告)日：1999-09-23
申请号：PCT/IL1999/000154
申请日：1999-03-18
Abstract: Method and modem for fast timing recovery of transmitted data between a master chi DSL modem and a slave chi DSL modem, over a noisy, high loss, high distortion wiring. Transmitted QAM symbols are received and sampled (10) at the slave modem. The sampled data is split into in-phase (I) and quadrature (Q) channels (11, 12), each of which is filtered by matched filter (13, 14). The filtered I and Q outputs are sampled at twice the symbol rate and the lower and upper band edge components are extracted by modulating each of the sampled sequence of I and Q outputs with two discrete time sequences: cos(0.5 pi n) = ...,1,0,-1,0,... and sin(0.5 pi n) = ...,0,1,0,-1,... Each of the resulting products is filtered with a first order low-pass filter (26, 27) and re-sampled again at the symbol rate. The Bit Error Rate is computed (28), and the slave modem switches from blind timing recovery mode, to data directed timing recovery mode, after the Bit Error Rate has sufficiently decreased.
Abstract translation: 用于在主i DSL调制解调器和从属i DSL调制解调器之间通过嘈杂，高损耗，高失真布线快速定时恢复传输数据的方法和调制解调器。 发射的QAM符号在从调制解调器处被接收和采样（10）。 采样数据被分成同相（I）和正交（Q）通道（11,12），每个通道由匹配滤波器（13,14）滤波。 滤波后的I和Q输出以符号速率的两倍进行采样，并通过用两个离散时间序列调制I和Q输出的每个采样序列来提取下限和上边沿分量：cos（0.5 pi n）= .. ...，1,0，-1,0，...和sin（0.5 pi n）= ...，0,1,0，-1，... ...每个产生的产品都以第一级低 - 通滤波器（26,27），并以符号速率重新采样。 计算位错误率（28），从调制解调器从盲定时恢复模式切换到数据定向定时恢复模式，在误码率已经足够降低之后。
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43.发明申请METHOD AND APPARATUS FOR GENERATING A PROBING SIGNAL FOR A SYSTEM HAVING NON-LINEAR NETWORK AND CODEC DISTORTION 审中-公开用于生成具有非线性网络和编码失真的系统的探测信号的方法和装置
公开(公告)号：WO99008413A2
公开(公告)日：1999-02-18
申请号：PCT/US1998/016725
申请日：1998-08-12
CPC classification number: H04L25/4927 , H04L1/242 , H04L5/1438 , H04L7/027 , H04L25/0226
Abstract: The present invention provides a method of generating a signal that may be used to determine the characteristic response of a communication channel that utilizes the public Digital Telephone Network (DTN). The channel includes the DTN, which may have Network Digital Attenuators (NDA) and/or Robbed Bit Signalling (RBS), and a Digital-to-Analog Converter (DAC), (also known as a codec), as well as the analog characteristics of the local loop, typically a twisted pair of copper wires. The present invention provides a method and apparatus to determine the optimal sampling instant of the received data stream. The present invention provides a probing signal that is well-suited for use in determining the channel's response to a known sequence of PCM codes used as data symbols. This is especially useful in so-called PCM modulation schemes that utilize the DTN, where knowledge of network and DAC distortion predicated the selection of available PCM codes used to represent data. This information is also useful when the data receiver, or PCM modem, makes determinations of which codes were actually sent.
Abstract translation: 本发明提供一种生成可用于确定利用公共数字电话网（DTN）的通信信道的特征响应的信号的方法。 该信道包括可以具有网络数字衰减器（NDA）和/或Robbed位信令（RBS）以及数模转换器（DAC）（也称为编解码器）的DTN，以及模拟 本地环路的特性，通常是双绞铜线。 本发明提供一种确定接收数据流的最佳采样时刻的方法和装置。 本发明提供了一种非常适合用于确定信道对用作数据符号的已知PCM码的序列的响应的探测信号。 这在使用DTN的所谓PCM调制方案中特别有用，其中网络和DAC失真的知识预示着用于表示数据的可用PCM代码的选择。 当数据接收器或PCM调制解调器确定实际发送哪些代码时，该信息也是有用的。
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44.发明申请A DELAY LOCK LOOP WITH TRANSITION RECYCLING FOR CLOCK RECOVERY OF NRZ RUN-LENGTH ENCODED SERIAL DATA SIGNALS 审中-公开具有NRZ延长编码的串行数据信号的时钟恢复的具有过渡循环的延迟锁定环
公开(公告)号：WO98044673A1
公开(公告)日：1998-10-08
申请号：PCT/US1998/004869
申请日：1998-03-16
CPC classification number: H04L7/027 , H04L7/0276
Abstract: A clock recovery circuit uses a pair of variable delay lines to recover clock from a non-return to zero (NRZ) data stream. If an incoming clock transition occurs in the NRZ data, it is passed through one delay line to the output. If no incoming transition occurs, the transition at the output of the first delay line is recycled back through the second delay line. The outputs of the first and second delay lines are combined so that a transition occurs at every possible transition instant, regardless of whether a transition is present in the incoming data at the corresponding time. This permits the benefits of a delay locked loop to be achieved when using NRZ data. Applications of the clock recovery circuits to gigabit data communications systems are described.
Abstract translation: 时钟恢复电路使用一对可变延迟线来从不归零（NRZ）数据流恢复时钟。 如果在NRZ数据中发生进入的时钟转换，则将其通过一条延迟线传送到输出。 如果没有进入转换，则第一延迟线的输出端的转换通过第二延迟线再循环回来。 第一和第二延迟线的输出被组合，使得在每个可能的转变瞬间发生转变，而不管在相应的时间在输入数据中是否存在转换。 这允许在使用NRZ数据时实现延迟锁定环路的优点。 描述了将时钟恢复电路应用于千兆数据通信系统。
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45.发明申请Synchronization method and receiver comprising multiplication means, transform and comparison means 审中-公开同步方法和接收机，包括乘法装置，变换和比较装置
公开(公告)号：WO9826512A3
公开(公告)日：1998-07-30
申请号：PCT/FI9700784
申请日：1997-12-12
Applicant: NOKIA TELECOMMUNICATIONS OY , ITKONEN JARKKO
Inventor： ITKONEN JARKKO
Abstract: The invention relates to a synchronization method and a receiver used in a radio system in which synchronization is made to a received signal, the radio system comprising at least one receiver (100, 200, 300) which receives modulated and partly previously known signal consisting of symbols and which signal contains time and frequency deviation. The receiver comprises multiplication means (402) for multiplying the received signal by the known part of the received signal for obtaining a product, transform means (403) for correlating the product in order to obtain a ratio and comparison means (404) for comparing the ratio with a pre-set correlation threshold value, on the basis of which comparison a decision is made on synchronization to the received signal.
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Patent Agency Ranking46.发明申请BIT AND FRAME SYNCHRONIZING UNIT FOR AN ACCESS NODE IN AN OPTICAL TRANSMISSION DEVICE 审中-公开用于光传输设备中访问节点的位和帧同步单元
公开(公告)号：WO9115907A3
公开(公告)日：1991-12-12
申请号：PCT/CH9100083
申请日：1991-04-08
Applicant: ASCOM TECH AG
Inventor： VOGEL PAUL , MARTINSON THOMAS
CPC classification number: H04L7/0075 , H04L7/027 , H04L7/0332 , H04L7/041 , H04L7/042 , H04L7/10
Abstract: The bit and frame synchronizing unit (51) described is designed to synchronize an access node with the bit stream passing along a fibre-optic cable. The unit (51) has an electrically controlled optical switch (57) used as a light switch. It also has a sequence indicator (75) for electrical control of the switch (57), an impulse generator (72), an electro-optical converter (60), an electrical integrator (63), an adjustment and weighting unit (66) and a control unit (69). The unit (51) also has a coarse-adjustment device (48). An optical bit pattern (BM) appears periodically at the input (53), and at the control input (44) an associated equivalent electrical reference pattern (VM). The size of the resultant electrical voltage pulse (U) at the output (64) of the integrator (63) is, in an approximately synchronous-running state, a measure of the phase difference between the two. In the case of perfect synchronization, a sharp impulse peak occurs. The unit (51) is intended for the simultaneous synchronization of bit and frame phase.
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公开(公告)号：WO2022124560A1
公开(公告)日：2022-06-16
申请号：PCT/KR2021/014536
申请日：2021-10-19
Inventor： 안준영 AHN, Joonyoung
Abstract: 전자 장치 및 이의 제어 방법이 개시된다. 본 개시의 전자 장치는 통신 인터페이스, 전자파 노이즈 신호를 검출하는 노이즈 센서, 메모리 및 제1 사용자 단말 장치로부터 동기화 요청 신호가 통신 인터페이스를 통해 수신되면, 노이즈 센서를 통해 제1 사용자 단말 장치의 전자파 노이즈 신호를 획득하고, 획득된 제1 사용자 단말 장치의 전자파 노이즈 신호의 주파수 대역 중 피크 노이즈를 포함하는 제1 주파수 대역 제1 사용자 단말 장치의 제1 식별 정보로서 메모리에 저장하고, 제1 사용자 단말 장치와의 동기화에 대응되는 동작을 수행할 수 있다.
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公开(公告)号：WO2022048247A1
公开(公告)日：2022-03-10
申请号：PCT/CN2021/100921
申请日：2021-06-18
Applicant: 深圳市朗强科技有限公司
Inventor： 高炳海
Abstract: 本申请公开了时钟频率同步方法、装置、设备及计算机存储介质，方法包括：接收设备通过第二通信模块获取由发送设备发送的UDP数据包，将UDP数据包存储于接收设备的缓存中，将缓存中UDP数据包的数据量的值与第一值进行运算，获得数据量的值与第一值之间的差值的绝对值；接收设备比较绝对值与预设阈值，如果绝对值大于预设阈值，则对接收设备中晶振的时钟频率调整，获得目标时钟频率，以使得调整后差值的绝对值小于或等于预设阈值，基于目标时钟频率与发送设备之间保持时钟频率同步；上述晶振包括：具有编程接口的晶体振荡器。采用本申请，可降低硬件成本，实现UDP数据包超低延时传输，也即，可实现高清视频高质量、低延时传输。
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公开(公告)号：WO2021221195A1
公开(公告)日：2021-11-04
申请号：PCT/KR2020/005591
申请日：2020-04-28
Applicant: 엘지전자 주식회사
Inventor： 하업성
Abstract: 본 발명은 신호 처리 장치 및 이를 구비하는 영상표시장치이다. 본 발명의 일 실시예에 따른 신호 처리 장치는, 베이스 밴드 신호를 다운 샘플링하는 샘플러와, 다운 샘플링된 데이터를 저장하는 메모리와, 메모리에 저장된 데이터를 독출하고, 독출된 데이터를 주파수 도메인에서 시프트시키는 주파수 시프터와, 시프트된 데이터에 기초하여, 심벌 레이트를 연산하는 심벌 레이트 연산부와, 연산된 심벌 레이트에 기초하여, 제1 캐리어 주파수 오프셋을 연산하는 제1 오프셋 연산부와, 연산된 제1 캐리어 주파수 오프셋에 기초하여, 제2 캐리어 주파수 오프셋을 연산하는 제2 오프셋 연산부와, 제2 캐리어 주파수 오프셋을 보상하는 오프셋 보상부를 포함한다. 이에 의해, 베이스 밴드 신호에 기초하여 복조 완료시까지의 시간을 단축할 수 있게 된다.
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