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    METHOD AND SYSTEM FOR CONTROLLING PHASE OF A SIGNAL
    1.
    发明申请
    METHOD AND SYSTEM FOR CONTROLLING PHASE OF A SIGNAL 审中-公开
    用于控制信号相位的方法和系统

    公开(公告)号：WO2015140610A1

    公开(公告)日：2015-09-24

    申请号：PCT/IB2014/066512

    申请日：2014-12-02

    Applicant: ARIEL-UNIVERSITY RESEARCH AND DEVELOPMENT COMPANY LTD.

    Inventor： STERNKLAR, Shmuel ,  BITON, Moran

    IPC: H04B10/548 ,  H04B1/04 ,  H04L5/12

    CPC classification number: H04B10/548 ,  G01S17/36 ,  H04B10/50577 ,  H04L27/361

    Abstract: A method of generating a signal being phase-shifted at a predetermined phase- shift division factor relative to a reference signal is disclosed. The method comprises: using the predetermined phase-shift division factor for selecting a modulation amplitude, modulating a control signal at the selected modulation amplitude, and combining the reference signal and the control signal to form the phase- shifted.

    Abstract translation: 公开了一种以相对于参考信号的预定相移分频系数相移的信号的方法。 该方法包括：使用预定的相移分频因子来选择调制幅度，以所选择的调制幅度调制控制信号，并组合参考信号和控制信号以形成相移。

    METHOD AND SYSTEM FOR MAPPING BIT SEQUENCES
    2.
    发明申请
    METHOD AND SYSTEM FOR MAPPING BIT SEQUENCES 审中-公开
    用于映射比特序列的方法和系统

    公开(公告)号：WO2013097088A1

    公开(公告)日：2013-07-04

    申请号：PCT/CN2011/084725

    申请日：2011-12-27

    Applicant: FRANCE TELECOM RESEARCH & DEVELOPMENT BEIJING COMPANY LIMITED ,  BAI, Baoming ,  ZHOU, Lin ,  LUO, Yajuan

    Inventor： BAI, Baoming ,  ZHOU, Lin ,  LUO, Yajuan

    IPC: H04L5/12

    CPC classification number: H04L27/02 ,  H04L1/0027 ,  H04L1/005 ,  H04L1/0057 ,  H04L1/0071 ,  H04L25/03318 ,  H04L25/067 ,  H04L27/34 ,  H04L27/3411 ,  H04L27/3433

    Abstract: A method of mapping a plurality of different bit sequences (u) to a plurality of different signal points (x) in a constellation, the number of bit sequences (u) being greater than the number of signal points (x), said method comprising, for a device in a telecommunication network, the acts of: - determining, for each signal point (x) in the constellation, a number of bit sequences (u) to be mapped to said each signal point (x), the numbers of bit sequences (u) being distributed according to a discrete Gaussian distribution among the constellation, - selecting in the plurality of bit sequences (u), f o r e a c h s i g n a l p o i n t (x) in the constellation, a set comprising the determined number of bit sequences (u) that minimize the maximal Hamming distance among the selected sets.

    Abstract translation: 一种将星座中的多个不同位序列（u）映射到多个不同信号点（x）的方法，比特序列（u）的数目大于信号点数（x），所述方法包括 对于电信网络中的设备，执行以下动作： - 对于星座中的每个信号点（x），确定要映射到所述每个信号点（x）的位序列（u）的数量， 根据星座中的离散高斯分布分配比特序列（u）， - 选择星座中的多个比特序列（u），前缀信号点（x），包括确定数量的比特序列（u）的集合， 最小化所选集合中的最大汉明距离。

    PROGRAMMABLE COMPUTE UNIT WITH INTERNAL REGISTER AND BIT FIFO FOR EXECUTING VITERBI CODE
    5.
    发明申请
    PROGRAMMABLE COMPUTE UNIT WITH INTERNAL REGISTER AND BIT FIFO FOR EXECUTING VITERBI CODE 审中-公开
    可编程计算机单元，具有内部寄存器和执行VITERBI代码的位FIFO

    公开(公告)号：WO2009042031A1

    公开(公告)日：2009-04-02

    申请号：PCT/US2008/010571

    申请日：2008-09-10

    Applicant: ANALOG DEVICES, INC. ,  WILSON, James ,  STEIN, Yosef ,  YUKNA, Gregory ,  LAHR, Lewis

    Inventor： WILSON, James ,  STEIN, Yosef ,  YUKNA, Gregory ,  LAHR, Lewis

    IPC: H04L5/12

    CPC classification number: H03M13/4107 ,  H03M13/4169

    Abstract: A programmable compute unit with an internal register with a bit FIFO for executing Viterbi code is configured to accumulate in the forward path the best-path to each state in an internal register and store the survivor trace back information bit for each state in each stage in a bit FIFO; and in the trace back, selecting the optimal best-path through the Viterbi trellis by tracing through the bit trace back information survivor bits beginning with the survivor bit of the last stage path; and generating in response to the Viterbi constrain length and a current bit FIFO address, the next bit FIFO address and decoded output bit for the next previous stage.

    Abstract translation: 具有用于执行维特比码的具有位FIFO的内部寄存器的可编程计算单元被配置为在前向路径中累积到内部寄存器中的每个状态的最佳路径，并且将每个状态中的每个状态的幸存回迹信息位存储在 一位FIFO; 并且在追溯中，通过跟踪通过从最后一级路径的幸存位开始的位追溯信息幸存者比特来选择通过维特比网格的最佳最佳路径; 并响应于维特比约束长度和当前位FIFO地址产生下一个位FIFO地址和下一个前一级的解码输出位。

    TOKEN PASSING DATA TRANSFER MECHANISM FOR RESERVATION BASED PROTOCOLS
    6.
    发明申请
    TOKEN PASSING DATA TRANSFER MECHANISM FOR RESERVATION BASED PROTOCOLS 审中-公开
    TOKEN通过数据传输机制进行基于预定的协议

    公开(公告)号：WO2009020551A1

    公开(公告)日：2009-02-12

    申请号：PCT/US2008/009279

    申请日：2008-08-01

    Applicant: STACCATO COMMUNICATIONS, INC.

    Inventor： HILLYARD, Jason

    IPC: H04L5/12

    CPC classification number: H04L1/1887

    Abstract: Establishing communication between a first device and a second device participating in a reservation based communication protocol over a communication network and sharing the reservation to allow for data to be transmitted from both devices during the reservation.

    Abstract translation: 通过通信网络建立参与基于预约的通信协议的第一设备和第二设备之间的通信，并共享预留以允许在预留期间从两个设备发送数据。

    VITERBI-DECODER BASED ADAPTIVE ARRAY PROCESSING METHOD AND SYSTEM
    7.
    发明申请
    VITERBI-DECODER BASED ADAPTIVE ARRAY PROCESSING METHOD AND SYSTEM 审中-公开
    基于VITERBI解码器的自适应阵列处理方法和系统

    公开(公告)号：WO2007070020A1

    公开(公告)日：2007-06-21

    申请号：PCT/US2005/005939

    申请日：2005-02-24

    Applicant: EFFICIENT SPECTRUM, INC.

    Inventor： ZANCEWICZ, Gregory

    IPC: G06N3/00 ,  H04L23/02 ,  H04L5/12

    CPC classification number: H04L1/0054 ,  H03M13/41 ,  H04L1/0047

    Abstract: The present invention improves the performance of adaptive antenna array processing systems. In particular, the present invention aims to optimize reception and transmission of signals that employ convolutional coding and Viterbi decoders. The present invention utilizes certain information from Viterbi decoders to improve the performance of a genetic algorithm in optimizing the reception and transmission of signals in an adaptive antenna array system.

    Abstract translation: 本发明改进了自适应天线阵列处理系统的性能。 特别地，本发明旨在优化采用卷积编码和维特比解码器的信号的接收和传输。 本发明利用来自维特比解码器的某些信息来改善遗传算法在优化自适应天线阵列系统中的信号的接收和传输方面的性能。

    A MEMORYLESS SPECTRUM CORRECTION ALGORITHIM FOR NON-IDEAL I/Q DEMODULATORS
    9.
    发明申请
    A MEMORYLESS SPECTRUM CORRECTION ALGORITHIM FOR NON-IDEAL I/Q DEMODULATORS 审中-公开
    非理想I / Q调制解调器的无记录校正算法

    公开(公告)号：WO2006057890A3

    公开(公告)日：2006-11-16

    申请号：PCT/US2005041689

    申请日：2005-11-17

    Applicant: COGNIO INC ,  SUGAR GARY L

    Inventor： SUGAR GARY L

    IPC: H04L5/12 ,  H04L27/06

    CPC classification number: H04L27/261 ,  H03D3/007 ,  H03D3/009

    Abstract: An algorithm for correcting the output of an analog I/Q demodulator (10) without the need for calibration or storing state information. The output of the analog I/Q demodulator (10) is digitized, and the discrete-time samples are divided into segments. A digital frequency transform (e.g., a Discrete Fourier Transform) (35) is computed for each segment. The effects of the non-ideal 1/Q demodulator are removed by identifying a set of image frequency candidates for each digital frequency transform, and for each image frequency candidate, estimating a set of demodulator imbalance parameters to characterize the demodulator imbalance at that frequency and correcting the digital frequency transform at the image frequency candidate using the imbalance parameters in order to minimize the effects of the imbalance. Each digital frequency transform is corrected independently and consequently no persistent state information needs to be saved between transforms.

    Abstract translation: 一种用于校正模拟I / Q解调器（10）的输出而不需要校准或存储状态信息的算法。 模拟I / Q解调器（10）的输出被数字化，离散时间采样被分成多个段。 为每个段计算数字频率变换（例如，离散傅里叶变换）（35）。 通过识别每个数字频率变换的一组图像频率候选，并且对于每个图像频率候选，去除非理想1 / Q解调器的影响，估计一组解调器不平衡参数以表征该频率处的解调器不平衡，以及 使用不平衡参数来校正图像频率候选的数字频率变换，以便最小化不平衡的影响。 每个数字频率变换被独立地校正，因此在转换之间不需要保存持久状态信息。

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