公开(公告)号：WO2022198210A1

公开(公告)日：2022-09-22

申请号：PCT/US2022/071171

申请日：2022-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： YANG, John ,  BHALGAT, Yash Sanjay ,  PORIKLI, Fatih Murat ,  CHANG, Simyung

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06V40/10

Abstract: Certain aspects of the present disclosure provide a method, including: processing input data with a feature extraction stage of a machine learning model to generate a feature map; applying an attention map to the feature map to generate an augmented feature map; processing the augmented feature map with a refinement stage of the machine learning model to generate a refined feature map; processing the refined feature map with a first regression stage of the machine learning model to generate multi-dimensional task output data; and processing the refined feature data with an attention stage of the machine learning model to generate an updated attention map.

公开(公告)号：WO2022197754A1

公开(公告)日：2022-09-22

申请号：PCT/US2022/020462

申请日：2022-03-15

Applicant: ILLUMINA SOFTWARE, INC.

Inventor： PARNABY, Gavin Derek

IPC: G06N3/04 ,  G06N3/063 ,  G16B40/20 ,  G16B30/00

Abstract: A method of quantizing parameters of a neural network includes grouping a plurality of parameters of a neural network in a plurality of groups. Each group of the plurality of groups includes corresponding two or more parameters of the plurality of parameters. In an example, for each group, a corresponding quantization format is selected from a plurality of available quantization formats, such that a first quantization format selected for at least a first group is different from a second quantization format selected for at least a second group. For each group, individual parameters within the corresponding group are quantized using the quantization format selected for the corresponding group. The quantized parameters of the plurality of groups are stored in a memory.

公开(公告)号：WO2022191879A1

公开(公告)日：2022-09-15

申请号：PCT/US2021/058266

申请日：2021-11-05

Applicant: POLYN TECHNOLOGY LIMITED ,  MASLOV, Boris

Inventor： TIMOFEJEVS, Aleksandrs ,  KOVSHOV, Nikolai ,  GODOVSKIY, Dmitri

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06F30/36

Abstract: Systems and methods are provided for analog hardware realization of convolutional neural networks for voice clarity. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents one or more connections between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component values for the analog components.

公开(公告)号：WO2022191083A1

公开(公告)日：2022-09-15

申请号：PCT/JP2022/009528

申请日：2022-03-04

Applicant: 株式会社Ｙｏｆｆｉｅ

Inventor： 河口　斉

IPC: G06N3/04 ,  G06N3/063

Abstract: 入力刺激に対する推論結果を出力する推論装置１であって、入力刺激に対応する入力信号に対し対応する出力信号を出力する第１の神経模倣回路を少なくとも一つ含む第１の神経模倣回路部１２と、入力刺激に対応する入力信号に対し対応する出力信号を出力する第２の神経模倣回路であって、同一の入力信号を入力したときに、第１の神経模倣回路とは異なる出力信号を出力する第２の神経模倣回路を少なくとも一つ含む第２の神経模倣回路部１３と、第２の神経模倣回路部１３に含まれる第２の神経模倣回路の少なくとも一部の出力信号に基づき、第１の神経模倣回路部１２に入力される、入力刺激に対応する入力信号を補正する相関回路部１４と、を有する。

公开(公告)号：WO2022174601A1

公开(公告)日：2022-08-25

申请号：PCT/CN2021/124343

申请日：2021-10-18

Applicant: 华为技术有限公司

Inventor： 胡明睿 ,  程康

IPC: G06N3/063

Abstract: 一种电池状态预测模型的训练方法及相关装置，所述方法根据目标电池的第一电池特征信息对第一模型进行自监督训练，第一模型包括第一预训练表示模型和第一预测模型；根据目标电池的第二电池特征信息和第一标签信息对电池状态预测模型进行监督训练，电池状态预测模型包括特征向量提取模型和第二预测模型，特征向量提取模型进行监督训练之前的初始参数包括对第一模型进行自监督训练后得到的第一预训练表示模型的参数。能够使用实车数据预测实车的电池状态，并且降低了电池状态预测模型的训练成本。

公开(公告)号：WO2022173538A1

公开(公告)日：2022-08-18

申请号：PCT/US2022/011815

申请日：2022-01-10

Applicant: INTEL CORPORATION

Inventor： KALSI, Gurpreet S ,  CHAKENALLI NANJEGOWDA, Ramachandra ,  PILLAI, Kamlesh R ,  SUBRAMONEY, Sreenivas

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: Embodiments are generally directed to techniques for accelerating neural networks. Many embodiments include a hardware accelerator for a bi-directional multi-layered GRU and LC neural network. Some embodiments are particularly directed to a hardware accelerator that enables offloading of the entire LC+GRU network to the hardware accelerator. Various embodiments include a hardware accelerator with a plurality of matrix vector units to perform GRU steps in parallel with LC steps. For example, at least a portion of computation by a first matrix vector unit of a GRU step in a neural network may overlap at least a portion of computation by a second matrix vector unit of an output feature vector for the neural network. Several embodiments include overlapping computation associated with a layer of a neural network with data transfer associated with another of the neural network.

公开(公告)号：WO2022154965A1

公开(公告)日：2022-07-21

申请号：PCT/US2021/065507

申请日：2021-12-29

Applicant: APPLE INC.

Inventor： MILLS, Christopher, L. ,  PARK, Sung, Hee

IPC: G06N3/063 ,  G06N3/04 ,  G06F7/24 ,  G06F7/544

Abstract: Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a convolution operation on input data in a first mode and a parallel sorting operation on input data in a second mode. The neural engine circuit includes a plurality of operation circuits and an accumulator circuit coupled to the plurality of operation circuits. The plurality of operation circuits receives input data. In the first mode, the plurality of operation circuits performs multiply-add operations of a convolution on the input data using a kernel. In the second mode, the plurality of operation circuits performs a portion of a parallel sorting operation on the input data. In the first mode, the accumulator circuit receives and stores first results of the multiply-add operations. In the second mode, the accumulator circuit receives and stores second results of the parallel sorting operation.

公开(公告)号：WO2022150009A1

公开(公告)日：2022-07-14

申请号：PCT/SG2021/050010

申请日：2021-01-08

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： TAN, Hong Meng Benjamin ,  MEFTAH, Souhail ,  AUNG, Khin Mi Mi

IPC: G06N3/04 ,  G06N3/063 ,  G06N20/00 ,  G06N99/00

Abstract: In some aspects, a set of input elements is obtained, at a rectified linear unit-activated neuron of a neural network based, on input data at the neuron. A first group and a second group of input elements are generated based on the set of input elements. The first group and the second group of input elements are associated with first weight elements and second weight elements, respectively. A first value is generated based on the first group of input elements and the first weight elements. A second value is generated based on the second group of input elements and the second weight elements. A third value and a fourth value are respectively generated based on a first operation and a second operation on the first value and the second value. An output of the neuron is generated based on the third value and the fourth value.

公开(公告)号：WO2022146955A1

公开(公告)日：2022-07-07

申请号：PCT/US2021/065268

申请日：2021-12-28

Applicant: X DEVELOPMENT LLC

Inventor： LASZLO, Sarah Ann ,  SCHILLINGS, Benoit ,  APTE, Raj B.

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for implementing brain emulation neural networks using analog circuits. One of the methods includes obtaining data defining a synaptic connectivity graph representing synaptic connectivity between neurons in a brain of a biological organism, wherein the synaptic connectivity graph comprises a plurality of nodes and edges, wherein each edge connects a pair of nodes, each node corresponds to a respective neuron in the brain of the biological organism, and each edge connecting a pair of nodes in the synaptic connectivity graph corresponds to a synaptic connection between a pair of neurons; determining an artificial neural network architecture corresponding to the synaptic connectivity graph; and generating, from the artificial neural network architecture, a design of an analog circuit that is configured to execute a plurality of operations of an artificial neural network having the artificial neural network architecture.

公开(公告)号：WO2022146467A1

公开(公告)日：2022-07-07

申请号：PCT/US2021/026233

申请日：2021-04-07

Applicant: OJO LABS, INC.

Inventor： LEVY, Joshua Howard ,  LEGAULT, Jacy Myles ,  CZECHOWSKI, Kenneth

IPC: G06N3/04 ,  G06N3/08 ,  G06N5/04 ,  G06N3/063 ,  G06N5/02 ,  G06N3/0427 ,  G06N3/0454 ,  G06N5/022 ,  G06N5/041

Abstract: A supervised learning processing (SLP) system and method provide cooperative operation of a network of supervised learning processors to concurrently distribute supervised learning processor training, generate predictions, provide prediction driven responses to input objects, and provide operational sequencing to concurrently control and distribute supervised learning processor training and provide predictive responses to input data. The SLP system can dynamically sequence SLP subsystem operations to improve resource utilization, training quality, and/or processing speed. A system monitor-controller can dynamically determine if process environmental data indicates initiation of dynamic subsystem processing sequencing. Concurrently training SLPs provides accurate predictions of input objects and responses thereto and enhances the network by providing high quality value predictions and responses and avoiding potential training and operational delays. The SLP system can enhance the network of SLP subsystems by providing flexibility to incorporate multiple SLP models into the network and train with concurrent commercial operations.