公开(公告)号：WO1993018387A1

公开(公告)日：1993-09-16

申请号：PCT/JP1993000277

申请日：1993-03-04

Applicant: FUJITSU LIMITED ,  NAKAJIMA, Eiichi ,  UDOH, Yasuo ,  IIKAWA, Tsutomu ,  KITAKOHJI, Toshisuke ,  MOTOYOSHI, Teruo ,  FURUSAWA, Takashi ,  YAMAZAKI, Shiori ,  NAKAYAMA, Masao ,  SATOH, Michiko ,  FUKUSHIMA, Shigeru

Inventor： FUJITSU LIMITED

IPC: G01N01/22

CPC classification number: G01N1/405 ,  G01N1/2214 ,  G01N1/2273

Abstract: A method of measuring an average long-term concentration of a specified gas in a certain environment accurately in a simplified manner with a small inexpensive apparatus by leaving a test piece such as metal, ceramic or metal salt to stand in an ambient atmosphere for a given period of time and analyzing the gas adsorbed thereby. In particular, NOx, CO2, and SO2 can be selectively adsorbed by, respectively, a porous metal or ceramic (transition metal oxide), a porous ceramic (rare earth element oxide), and a specified chloride such as copper chloride or silver chloride. The invention also discloses a test kit containing the test piece put in a case, and a protective case, umbrella and forced draft unit for putting the kit to practical use.

Abstract translation: 通过将诸如金属，陶瓷或金属盐的试验片放置在环境气氛中放置给定的方法，以简单的方式以简单的方式在一定环境中精确地测量特定气体的平均长期浓度的方法， 并分析其吸附的气体。 特别地，可以通过多孔金属或陶瓷（过渡金属氧化物），多孔陶瓷（稀土元素氧化物）和特定氯化物如氯化铜或氯化银选择性地吸附NOx，CO 2和SO 2。 本发明还公开了一种包含放置在壳体中的试验片的测试试剂盒，以及用于将试剂盒实际使用的保护壳，伞和强制通风单元。

公开(公告)号：WO1993014574A1

公开(公告)日：1993-07-22

申请号：PCT/JP1993000013

申请日：1993-01-08

Applicant: FUJITSU LIMITED ,  MORIYAMA, Junichi

Inventor： FUJITSU LIMITED

IPC: H04B01/74

CPC classification number: H04L1/22 ,  H04B1/74 ,  H04B10/032

Abstract: In an optical transmission system, on both transmitting and receiving sides, provided are respectively an auxiliary transmitter and a plurality of live transmitters. By connecting the main optical transmitting/receiving circuits of the auxiliary and live transmitters to an optical transmission line, transmitted are optical signals between the transmitting and receiving sides. In the optical transmission system, provided are an additional optical transmission line and control means. Via the additional optical transmission line, optical signals, produced by combining the outputs of optical transmitting sub-circuits of the live transmitters on the transmitting and receiving sides, are fed to optical receiving sub-circuits of the auxiliary transmitters. Also, via the additional transmission line, the optical signals outputted from optical transmitting sub-circuits of the auxiliary transmitters on both transmitting and receiving sides, are fed to the optical receiving sub-circuits of the live transmitters. In normal transmission by the live transmitters, the control means operates one of the optical receiving sub-circuits of the live transmitters. The control means selects one of the optical transmitting sub-circuits of live transmitters and operates the selected one in succession. However, if the selected sub-circuit of the live transmitters has a failure, the control means does not operate it and selects another optical transmitting sub-circuit. Also, the auxiliary transmitters detect the circuit quality between the auxiliary transmitters and the live transmitters.

Abstract translation: 在光传输系统中，在发射和接收侧，分别提供辅助发射机和多个直播发射机。 通过将辅助和实时发射机的主要光学发射/接收电路连接到光传输线路，传输的是发射侧和接收侧之间的光信号。 在光传输系统中，提供了附加的光传输线路和控制装置。 通过附加光传输线路，将发射和接收侧的实况发射机的光发射子电路的输出组合而产生的光信号馈送到辅助发射机的光接收子电路。 此外，经由附加传输线，从发射侧和接收侧的辅助发射机的光发射子电路输出的光信号被馈送到直播发射机的光接收子电路。 在实时发射机的正常传输中，控制装置操作实时发射机的光接收子电路之一。 控制装置选择现场发射机的光发射子电路中的一个，并连续地操作所选择的子电路。 然而，如果实时发射机的所选择的子电路发生故障，则控制装置不工作，并选择另一个光发送子电路。 此外，辅助发射机检测辅助发射机和实时发射机之间的电路质量。

公开(公告)号：WO1993014493A1

公开(公告)日：1993-07-22

申请号：PCT/JP1992001694

申请日：1992-12-25

Applicant: FUJITSU LIMITED ,  KANEGAE, Masahide

Inventor： FUJITSU LIMITED

IPC: G11B05/09

CPC classification number: G11B20/10046 ,  A63C17/064 ,  A63C17/226 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10009

Abstract: A circuit for equalizing the waveform of signal reproduced by a thin film magnetic head, which removes the negative edge of the waveform regardless of variation of the characteristics of the heads. In the equalizing circuit, an arithmetic circuit (7) receives the inputted read-out signal including negative edges and outputted from a thin film magnetic head, and equalizes the waveform of the inputted signal of a selected head (1) among thin film magnetic heads, using the following three output signals: the output of delay circuits (2, 3) whose input sides are terminated by means of characteristic impedances and which delay the inputted signal by a time tau 2, the output of a multiplying circuit (4) for multiplying the signal which is delayed by a time ( tau 2 - tau 1) by a value K1, and the output of a variable delay-time circuit (6) for delaying the inputted signal so as to remove the negative edges. The equalizing circuit is further provided with a delay setting circuit (8) which sets the delay time of the variable delay-time circuit (6) according to the signal representing the position of the head (1) and the head selecting signal. The delay time is controlled by the delay time specifying signal of the delay time setting circuit (8).

Abstract translation: 用于均衡由薄膜磁头再现的信号的波形的电路，其消除波形的负边缘，而与头的特性的变化无关。 在均衡电路中，运算电路（7）接收包括负边缘的输入的读出信号并从薄膜磁头输出，并将所选择的磁头（1）的输入信号的波形在薄膜磁头 ，使用以下三个输出信号：输入端通过特性阻抗终止并且将输入信号延迟时间τ2的延迟电路（2,3）的输出，乘法电路（4）的输出用于 将延迟了时间（τ2-τ1）的信号乘以值K1和用于延迟输入信号的可变延迟时间电路（6）的输出，以便去除负沿。 均衡电路还设置有延迟设置电路（8），其根据表示头部（1）的位置和头部选择信号的信号来设置可变延迟时间电路（6）的延迟时间。 延迟时间由延迟时间设定电路（8）的延迟时间指定信号控制。

公开(公告)号：WO1993012026A1

公开(公告)日：1993-06-24

申请号：PCT/JP1992001616

申请日：1992-12-10

Applicant: FUJITSU LIMITED ,  FUJITA, Nobuo ,  SASAKI, Sigenori ,  KAWASHIMA, Masato

Inventor： FUJITSU LIMITED

IPC: B65H29/58

CPC classification number: G03G15/234 ,  B65H29/58 ,  B65H2301/33312

Abstract: A sheet paper conveyor so assembled in a recording apparatus as to effect selective double-face recording on sheet paper includes a sheet feed path (20) for supplying sheet paper to a recording portion (14) of the recording apparatus, a sheet discharge path (22) for discharging sheet paper recorded at the recording portion of the recording apparatus, and a sheet bypass path (24) extending between the sheet feed path and the sheet discharge path. A sheet switch (26) is disposed at a branch portion between the sheet discharge path and the sheet bypass path, and sheet conveyor rollers (38a; 38b, 40a; 40b, 42a; 42b) capable of reverse driving so as to convey sheet paper in both directions are disposed in the sheet discharge path. The sheet conveyor rollers are disposed downstream of the sheet switch in the discharging direction of the sheet, and sheet paper recorded on one of the surfaces thereof at the recording portion of the recording apparatus is once conveyed by forward driving of the sheet conveyor rollers along the sheet discharge path, is then conveyed in the sheet bypass path through the sheet switch by reverse driving of the rollers, and thus causes reversion of sheet paper.

公开(公告)号：WO1993008598A1

公开(公告)日：1993-04-29

申请号：PCT/JP1992001354

申请日：1992-10-19

Applicant: FUJITSU LIMITED ,  ISODA, Yutaka

Inventor： FUJITSU LIMITED

IPC: H01L21/82

CPC classification number: H01L27/0211 ,  G06F17/505

Abstract: A method for optimizing the delay time of an LSI having latch circuits on its input and output sides. In the method, from combinational circuits provided between the plural latch circuits for outputting the data relevant to input data according to a clock, separated are plural logical circuits. Then, the delay times of the paths between the plural latch circuits of end points and the plural latch circuits of starting points are calculated respectively. Further, weightings of the separated logical circuits placed between all the starting points and all the end points, associated with the delay times, are performed for every path. Moreover, relative indexes for altering the delay times according to the weightings are calculated for every logical circuit.

Abstract translation: 一种用于优化在其输入和输出侧具有锁存电路的LSI的延迟时间的方法。 在该方法中，由多个锁存电路之间提供的用于输出与输入数据有关的数据的组合电路根据时钟而分离的组合电路是多个逻辑电路。 然后，分别计算端点的多个锁存电路与起始点的多个锁存电路之间的路径的延迟时间。 此外，对于每个路径执行放置在与延迟时间相关联的所有起始点和所有终点之间的分离逻辑电路的加权。 此外，针对每个逻辑电路计算根据加权改变延迟时间的相对索引。

公开(公告)号：WO1993008562A2

公开(公告)日：1993-04-29

申请号：PCT/JP1992001363

申请日：1992-10-20

Applicant: FUJITSU LIMITED ,  MIZOSHITA, Yoshifumi ,  KOSHIKAWA, Takao ,  KANAI, Hitoshi ,  KANE, Junichi ,  OTSUKA, Yoshinori ,  IKEGAWA, Yukinori

Inventor： FUJITSU LIMITED

IPC: G11B05/39

CPC classification number: G11B5/3916 ,  G11B5/02 ,  G11B5/3183 ,  G11B5/3903 ,  G11B5/3925 ,  G11B5/3967 ,  G11B19/04

Abstract: Head having an MR layer (26) in a space (101) formed by shield layers (28, 33) by providing a distance enough to protect magnetic flux flowing through the MR layer from a recording medium through a gap (51) formed by the shield layers, from leaking out to the shield layers and a flux guide (25) provided between the MR layer and the gap, having an end magnetically connected to the MR, extending over an effective area of the MR head, and another end having a width a little narrower than a width of track of the recording medium. A side of the MR layer, opposite to the side connected with the flux guide layer is placed in a narrow space (102) formed at a corner of the space. Magnetic flux leaked from the gap due to a sense current flowing through the MR layer is eliminated by making a current flow through a recording coil layer or through an electrically conductive layer placed in the space.

Abstract translation: 头部具有由屏蔽层（28,33）形成的空间（101）中的MR层（26），通过提供足够的距离来保护从记录介质流过MR层的磁通量通过由 屏蔽层，泄漏到屏蔽层和设置在MR层和间隙之间的磁通引导件（25），其具有磁性地连接到MR的端部，延伸在MR磁头的有效区域上，另一端具有 宽度比记录介质的轨道宽度稍窄。 MR层的与与磁通引导层连接的一侧相对的一侧被放置在形成在该空间的角部的窄空间（102）中。 通过使流过记录线圈层的电流或通过放置在该空间中的导电层而消除由于流过MR层的感测电流而从间隙泄漏的磁通。

公开(公告)号：WO1993005578A1

公开(公告)日：1993-03-18

申请号：PCT/JP1992001086

申请日：1992-08-27

Applicant: FUJITSU LIMITED ,  YAHAGI, Shinya ,  KOMATSU, Noriyoshi ,  KIBAYASHI, Toshimitsu ,  TODA, Yoshifumi

Inventor： FUJITSU LIMITED

IPC: H03L07/18

CPC classification number: H03L1/026 ,  H03L7/0891 ,  H03L7/107 ,  H03L7/189

Abstract: A frequency synthesizer comprising a phase-locked loop, wherein the phase of a comparison signal based on the output of a voltage controlled oscillator (7) is compared with the phase of a reference signal based on the output of a reference oscillator (1) by a phase comparator (3), and the phase difference signal is passed through a loop filter (50) and is used as a signal for controlling the voltage controlled oscillator. The frequency synthesizer is provided with a preset circuit (60) for changing the output of the voltage controlled oscillator by charging/discharging quickly a capacitor in the loop filter, and a changing circuit (70) for changing the time constant of the loop filter. By decreasing the time constant of the loop filter when the output frequency is changed, the phase-locked loop is phase-locked at a high speed.

Abstract translation: 一种频率合成器，包括锁相环，其中基于压控振荡器（7）的输出的比较信号的相位与参考信号的相位基于参考振荡器（1）的输出相比较，基准振荡器 相位比较器（3），相位差信号通过环路滤波器（50），并用作控制压控振荡器的信号。 该频率合成器设置有预置电路（60），用于通过对环路滤波器中的电容器进行快速充电/放电来改变压控振荡器的输出;以及改变电路（70），用于改变环路滤波器的时间常数。 通过在输出频率变化时减小环路滤波器的时间常数，锁相环以高速锁相。

公开(公告)号：WO1993003436A1

公开(公告)日：1993-02-18

申请号：PCT/JP1992000996

申请日：1992-08-05

Applicant: FUJITSU LIMITED ,  HAYASHI, Katzumi ,  MITANI, Masaaki ,  SHIMOGAI, Yoshinori

Inventor： FUJITSU LIMITED

IPC: G06F12/00

CPC classification number: G06F9/52 ,  G06F12/08

Abstract: A method for reducing the lock period of a shared buffer in a data processing system. This method comprises the step ( 3 ) of reserving a copy memory (18) when the content of a shared buffer ( 17 ) is rendered non-volatile, the step ( 4 ) of locking temporarily the shared buffer as an object, the step ( 5 ) of copying the content of the buffer to be rendered non-volatile to the copy memory, the step ( 6 ) of unlocking the shared buffer after copying to the copy memory, and the step ( 8 ) of rendering the content of the copy memory non-volatile. The shared buffer as the object is locked before the content of the shared buffer is copied into the copy memory, and after copying is completed and before the content of the copy memory is rendered non-volatile, the shared buffer is unlocked (that is, release of lock).

公开(公告)号：WO1992022825A1

公开(公告)日：1992-12-23

申请号：PCT/JP1992000721

申请日：1992-06-04

Applicant: FUJITSU LIMITED ,  OTA, Eikichi ,  KOMATA, Asao

Inventor： FUJITSU LIMITED

IPC: G01S13/28

CPC classification number: G01S13/288

Abstract: In a pulse compression system using a code series having a self correlation function, which has a sharp peak at a certain point and low side lobes, the number of kinds of usable code series is increased while permitting the level of the side lobes to a certain extent. This system uses a code series having a higher side lobe level of self correlation than an ideal code series as a transmission code series, modulates pulses by this transmission code series, in a primary modulation unit (1), receives and demodulates the pulses in a demodulation unit (2), modulates the demodulated output by a key code series or the difference between the ideal code series and the transmission code series to convert it to the ideal code series in a secondary modulation unit (3), and executes pulse compression processing of this ideal code series in a self correlation processing unit (4).

公开(公告)号：WO1992016892A1

公开(公告)日：1992-10-01

申请号：PCT/JP1992000296

申请日：1992-03-12

Applicant: FUJITSU LIMITED ,  KUROIWA, Koichi

Inventor： FUJITSU LIMITED

IPC: G06F07/52

CPC classification number: G06F7/535 ,  G06F7/4873 ,  G06F7/5375

Abstract: A floating-point dividing circuit for dividing floating-point data by a nonrecovery dividing method. The circuit has a circuit part (83) which pre-processes a dividend (N) and a divisor (D) before dividing and determines a division type, an exponent operating part (91), a mantissa dividing part (100), a quotient generating circuit part (93, 94, 101, 103-105), and at least one of an exception and non-operation detecting part (92) and a control part (90). The exception and non-operation detecting part (92) generates a stop signal (DSTOP#X) upon detecting a non-operation pattern, and stops the repeated operation of the mantissa dividing part (100). The control part (90) generates at least one of a non-execution signal (DRUN) and a control signal (DCNT0-15#X), and stops latch operations of registers, during the non-execution of a division instruction.