公开(公告)号：WO1992015935A1

公开(公告)日：1992-09-17

申请号：PCT/JP1992000221

申请日：1992-02-28

Applicant: FUJITSU LIMITED ,  MASE, Tomonori

Inventor： FUJITSU LIMITED

IPC: G06F03/06

CPC classification number: G06F3/0601 ,  G06F2003/0697 ,  G11B15/6835 ,  G11B15/689 ,  G11B17/228 ,  G11B27/002 ,  G11B27/36 ,  G11B2220/41 ,  G11B2220/90

Abstract: A library device (101) for moving a medium (56) by an accessor section (52) from a cell of plural cells (11), whose address is specified by a host computer (100), to a drive (12, 54), and for recording/reproducing information on/from the medium (56) by the drive (12, 54), includes a cell address conversion table (15) which stores real addresses (21) in correspondence with the addresses of the respective cells (11), and a converting means (61, 63) which converts the cell address (20) specified by the host computer (100) to a real address (21) indicating the position of the real cell (11) in the library device (101) by regarding the cell address (20) as a virtual address, and by referring to the cell address conversion table (15).

公开(公告)号：WO1992014321A1

公开(公告)日：1992-08-20

申请号：PCT/JP1992000098

申请日：1992-01-31

Applicant: FUJITSU LIMITED ,  TAKASE, Tadahiro ,  HAJIKANO, Kazuo ,  KAWASAKI, Takeshi ,  SHIMOE, Toshio ,  TACHIBANA, Tetsuo ,  HAGIHARA, Teruaki ,  KAKUMA, Satoshi ,  MURAYAMA, Masami ,  TAKECHI, Ryuichi ,  KUROYANAGI, Satoshi ,  KAMOI, Jyoei ,  TOMONAGA, Hiroshi

Inventor： FUJITSU LIMITED

IPC: H04L12/66

CPC classification number: H04L12/5602 ,  H04L2012/5616 ,  H04L2012/562 ,  H04L2012/5627 ,  H04L2012/563 ,  H04L2012/5645 ,  H04L2012/5652 ,  H04Q11/0478 ,  Y10S370/905

Abstract: Local connectionless information (data transferred directly without establishing a path to the destination) such as data of a local area network (LAN) is contained in an asynchronous transfer mode (ATM) network which uses a connection-oriented communication system (a system in which data is transferred after confirming the establishment of a path to the destination), and efficient, high speed routing can be made. Provided are a means (30) for cellulating/restoring connectionless information which bidirectionally performs conversion from the connectionless information to the connectionless cell of a fixed-length cell, and vice versa, a routing control means (31) which analyzes the destination address of the information in the connectionless cell and controls the routing of the cell, and an ATM network (32) which connects the means (30) with the means (31) by a permanent virtual channel of a fixed path, and connects the means (31) with each other by a permanent virtual channel of a fixed path or by a virtual channel of a semifixed path. Thus, connectionless information is divided into cells, and the exchange of each cell can be performed in an ATM network.

公开(公告)号：WO1992013344A1

公开(公告)日：1992-08-06

申请号：PCT/JP1992000050

申请日：1992-01-22

Applicant: FUJITSU LIMITED ,  FUJITSU VLSI LIMITED ,  NAKAGUCHI, Yukimi

Inventor： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

IPC: G11B20/18

CPC classification number: G11B20/1833 ,  G06F11/10 ,  H03M13/151

Abstract: An arithmetic operation processing method in an error correction processing device which is designed for high-speed chain search operation without increasing hardware quantity to reduce the time for correction processing. The error correction processing device has arithmetic circuits (141 to 159) that find solutions of the terms corresponding to the terms of an error position polynomial in which the elements read out from a recording medium are calculated from the data of code language consisting of Galois body, wherein the circuits (141 to 159) successively calculate values of terms for the variables consisting of Galois body of the polynomial in synchronism with the clock signals, the values of terms from the circuits (141 to 159) are added up through an EOR circuit (160) to find a solution of said error position polynomial, and presence or absence of error at the positions of the data is detected based on the solution, and wherein operations of said circuits (141 to 159) are carried out to successively find the solutions from the lower position through up to the upper position in said data that are read out.

Abstract translation: 一种误差校正处理装置中的算术运算处理方法，其被设计用于高速链路搜索操作，而不增加硬件数量以减少校正处理的时间。 误差校正处理装置具有运算电路（141〜159），其求出与由伽罗瓦体组成的代码语言的数据计算出的从记录介质读出的元素的误差位置多项式项对应的项的解 ，其中电路（141至159）与时钟信号同步地连续地计算由多项式的伽罗瓦体组成的变量的项的值，来自电路（141至159）的项的值通过EOR电路相加 （160）以找到所述错误位置多项式的解，并且基于该解决方案检测在数据位置处的有无错误，并且其中执行所述电路（141至159）的操作以依次找到 从读出的所述数据中的较低位置到上位置的解决方案。

公开(公告)号：WO1992009144A1

公开(公告)日：1992-05-29

申请号：PCT/JP1991001579

申请日：1991-11-19

Applicant: FUJITSU LIMITED ,  SUGAWARA, Takao ,  MIZOSHITA, Yoshifumi ,  AIKAWA, Takashi ,  MUTOH, Hiroshi ,  KASAI, Kiichirou

Inventor： FUJITSU LIMITED

IPC: H03M13/12

CPC classification number: H03M13/39

Abstract: A maximum likelihood decoding method for decoding the input signal subjected to wave interference. The input signals of several bits are sampled which are located before in time the assumed data string stored in an assumed path memory (104). By using this sampled values, the interference quantity with future signals located after in time the assumed data string is estimated. On reference to this interference quantity, the assumed sampled values of the input signals are calculated. By using these assumed sampled values and the sampled values of the input signals, the input signals are subjected to maximum likelihood decoding to generate a plurality of surviving paths and to store them in a path memory (102). Thereafter, the data of the most likelihood surviving path is outputted as a decoded data string.

Abstract translation: 用于对经受波干扰的输入信号进行解码的最大似然解码方法。 几个比特的输入信号被采样，其位于假定数据串之前的时间内，该假定数据串存储在假设的路径存储器（104）中。 通过使用这个采样值，估计在假定数据串之后的未来信号的干扰量。 参考该干扰量，计算输入信号的假定采样值。 通过使用这些假设的采样值和输入信号的采样值，对输入信号进行最大似然解码以产生多个幸存路径并将其存储在路径存储器（102）中。 此后，将最可能幸存路径的数据作为解码数据串输出。

公开(公告)号：WO1992008190A1

公开(公告)日：1992-05-14

申请号：PCT/JP1991001460

申请日：1991-10-25

Applicant: FUJITSU LIMITED ,  YOSHITAKE, Akihiro

Inventor： FUJITSU LIMITED

IPC: G06F09/38

CPC classification number: G06F9/30167 ,  G06F9/30163

Abstract: When a decoder (412; 63) for decoding the addressing field of an instruction outputs an indication of calculating addresses, in the case wherein a decoded instruction has both of an explicit indication of calculating addresses and an implicit indication of calculating addresses, the decoder (412; 63) determines, according to the instruction code, that either the explicit indication or the implicit one is to be performed in advance (Fig. 3A, Fig. 3B), and outputs those in order. Thereby, an instruction having an explicit indication of calculating addresses and an implicit one can be interpreted and executed at a high speed by an efficient pipeline processing.

公开(公告)号：WO1992007453A1

公开(公告)日：1992-04-30

申请号：PCT/JP1991001411

申请日：1991-10-16

Applicant: FUJITSU LIMITED ,  KAETSU, Mitsuo ,  MINEMATSU, Kiyoshi ,  YAMAJI, Hiroshi ,  HONGOH, Tomoyuki

Inventor： FUJITSU LIMITED

IPC: H05K07/14

CPC classification number: H05K7/1455 ,  H05K7/1404

Abstract: An apparatus for connecting tentatively which is used for electronic devices and makes the mounting of an electronic circuit unit possible only when the relative positions of a recessed part (25), which is provided at an edge part (21) of a shelf (11), and a protruding part (33), which is provided on the electronic circuit unit, coincide with each other. On a print-circuit board (45), at both the ends of which connectors (47, 49) are provided respectively, guide members (51, 53), which have guide grooves (55, 65) guiding both the side edges of the electronic circuit unit (27) respectively, are provided. A plurality of slidable rod members (61, 63) are provided in the guide member (51). When mounting the electronic circuit unit, the rod member (61 or 63) is made to slide by the protruding part (33). When the relative positions of the protruding rod member (63) and the recessed part (25) of the shelf (11) do not coincide with each other, this apparatus (43) for connecting tentatively cannot be mounted on the shelf (11).

公开(公告)号：WO1992006435A1

公开(公告)日：1992-04-16

申请号：PCT/JP1991001305

申请日：1991-09-27

Applicant: FUJITSU LIMITED ,  SUGAHARA, Hirohide ,  TAKAHASHI, Hajime ,  KABEMOTO, Akira ,  NAKAGAWA, Hideki

Inventor： FUJITSU LIMITED

IPC: G06F15/16

CPC classification number: G06F13/362 ,  G06F15/17

Abstract: A message control system in a data communication system in the form of a loosely coupled multiprocessing system in which a plurality of processing modules having memory units are connected to each other via a system bus. In the message control system, a memory unit (12) in each processing module has a data processing unit (14) which is a software which runs on a central processing unit (11) of the processing module, and buffers (16, 17) for storing messages to be transmitted. Further, a connection unit (13) in each processing module (10) includes at least a plurality of logic transmission ports (21) that successively read messages developed on the buffers (16, 17) and transmit them as a continuous message, a plurality of logic reception ports (22) for storing messages, a transmission system connection means (23) and a reception system connection means (24).

Abstract translation: 消息控制系统技术领域本发明涉及一种消息控制系统，其用于数据传输系统中并且是松耦合多处理器系统的形式，其中多个具有存储单元的处理模块连接在 他们通过系统总线。 在消息控制系统中，每个处理模块中的存储器单元（12）具有由在处理模块的CPU（11）上运行的软件组成的数据处理单元（14），以及 缓冲器（16,17），用于存储要发送的消息。 另外，每个处理模块（10）中的连接单元（13）至少包含多个逻辑发送端口（21），所述多个逻辑发送端口（21）依次执行读取在缓冲器（16,17）上发展的消息并将它们发送 以连续消息的形式，用于存储消息的多个逻辑接收端口（22），用于传输系统的连接成员（23）和用于接收系统的连接成员（24）。

公开(公告)号：WO1992006057A1

公开(公告)日：1992-04-16

申请号：PCT/JP1991001325

申请日：1991-10-02

Applicant: FUJITSU LIMITED ,  HIDAKA, Yuji ,  KIMURA, Makoto

Inventor： FUJITSU LIMITED

IPC: C06F13/10

CPC classification number: G06F13/126 ,  G06F13/24 ,  G06F13/4059

Abstract: A system for controlling the issues of input/output instructions applicable to a data processing system which includes a processor module having a CPU and adaptor modules which are in connection with the processor module by a system bus and control input/output devices according to the input/output instructions issued from the processor module. While the CPU executes other instructions after issuing the input/output instructions, the adaptor modules execute the input/output instructions and transfer the results of processing to the processor module. When the results sent from the adaptor modules are not normal, the CPU receives interrupt requests to provide the results of processing in the adaptor modules.

公开(公告)号：WO1992005581A1

公开(公告)日：1992-04-02

申请号：PCT/JP1991001221

申请日：1991-09-13

Applicant: FUJITSU LIMITED ,  ANDO, Yukio

Inventor： FUJITSU LIMITED

IPC: H01L23/00

CPC classification number: H01L21/67356 ,  H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device provided with a main body (10) of a rectangular package, many leads (12) protruded therefrom, a heat radiating fin assembly provided on the upper surface of the main body of the package. The assembly comprises a pole (14a) extending upright from the upper surface of the main body of the package, and at least one heat radiating fin (14b) extended from the pole perpendicularly. The heat radiating fins are supported by the direct or indirect engagement with a case (18) containing the semiconductor device. This support is so accomplished that no lead is in contact with anything. Also, when the semiconductor device is so disposed in the case in a predetermined direction, the direction canot be altered.

公开(公告)号：WO1992005577A1

公开(公告)日：1992-04-02

申请号：PCT/JP1991001262

申请日：1991-09-20

Applicant: FUJITSU LIMITED ,  KONDO, Makoto ,  SEKIGUCHI, Hiroshi

Inventor： FUJITSU LIMITED

IPC: H01L21/205

CPC classification number: C23C16/45561 ,  C30B25/14 ,  Y10S438/935

Abstract: Compound semiconductor crystals are grown through the organometallic vapor phase epitaxial method vertically by supplying the epitaxial gas divided into a plurality of flows so that each flow rate is adjusted from sub-injectors (11) arranged to cover the entire surface of a substrate (3) to grow crystals to the entire surface of the substrate (3). The method and apparatus of the present invention are effective especially for growth of quaternary III-V compound semiconductor crystals.