-
1.发明申请
公开(公告)号：WO2023084180A1
公开(公告)日：2023-05-19
申请号：PCT/GB2022/052395
申请日：2022-09-22
Inventor： HELLMAN, Ryan A , PARIKH, Viral , MARU, Siddharth , DAS, Tejasvi
Abstract: Circuitry comprising: a voltage monitoring path; a current monitoring path; a reference element of a predefined impedance; and processing circuitry, wherein in operation of the circuitry in a calibration mode of operation: the voltage monitoring path is operative to output a signal indicative of a voltage across the reference element in response to a reference signal applied to the reference element; the current monitoring path is operative to output a signal indicative of a current through the reference element in response to the reference signal; and the processing circuitry is operative to: receive the signal indicative of the voltage across the reference element and the signal indicative of the current through the reference element; generate an estimate of an impedance of the reference element; and determine a compensation parameter for an element of the circuitry for compensating for a difference between the estimate of the impedance and the predefined impedance of the reference element.
-
公开(公告)号：WO2023021268A1
公开(公告)日：2023-02-23
申请号：PCT/GB2022/052045
申请日：2022-08-03
Inventor： LESSO, John Paul , IDO, Toru , DOY, Anthony S.
IPC: H02J7/00
Abstract: Balancing circuitry for balancing cells in first and second modules of a battery pack, wherein the first module comprises a first plurality of cells and the second module comprises a second plurality of cells, the balancing circuitry comprising: first cell balancing circuitry operative to balance the first plurality of cells of the first module; and second cell balancing circuitry operative to balance the second plurality of cells of the second module, wherein the second cell balancing circuitry is further operative to balance at least one cell of the first plurality of cells of the first module with at least one cell of the second plurality of cells of the second module.
-
公开(公告)号：WO2022248822A1
公开(公告)日：2022-12-01
申请号：PCT/GB2022/050699
申请日：2022-03-21
Inventor： WHYTE, Neil , BREWSTER, Andy , BLACK, Angus
Abstract: A device (400) comprising: a data interface comprising: a data input (DATA) for receiving a data signal; a clock input (CLK) for receiving a clock signal for clocking the data signal; and a timing input (FSYNC) for receiving a first timing signal having a first freguency; and a timing signal generator (404) configured to generate, based on the first timing signal (FSYNC) and the data signal (DATA), a second timing signal (DT) having a second freguency, the first freguency (FSYNC) being a integer multiple of the second freguency (DT), a phase of the second timing signal (DT) being aligned with an event in the data signal (DATA).
-
公开(公告)号：WO2022185029A1
公开(公告)日：2022-09-09
申请号：PCT/GB2022/050452
申请日：2022-02-18
Inventor： LESSO, John Paul
Abstract: An amplifier circuitry (300) includes a linear amplifier stage (110) that receives an input signal and outputs a first drive signal to an output node (302) and a switching amplifier stage (130) operable to output a second drive signal to the output node (302). A controller (340) is selectively operable in a first dual-amplifier mode, in which switching of the switching amplifier stage is controlled based on a current of the first drive signal, such that the current of the first drive signal does not exceed a first current threshold magnitude; and at least one other mode, in which the controller controls the switching amplifier stage such that the current of the first drive signal may exceed the first current threshold magnitude. The controller (340) selectively controls the mode of operation based on an indication (SSL) of signal level of the output signal.
-
公开(公告)号：WO2022106804A1
公开(公告)日：2022-05-27
申请号：PCT/GB2021/052384
申请日：2021-09-15
Inventor： LESSO, John Paul , DOY, Anthony Stephen
Abstract: The present disclosure relates to circuitry for driving a capacitive load. The circuitry comprises pre-processor circuitry configured to process an input signal to generate a processed signal; driver circuitry coupled to the pre-processor circuitry and configured to generate a drive signal, based on the processed signal, for driving the capacitive load; and processor circuitry configured to determine a resonant frequency of the capacitive load. The pre-processor circuitry is configured to process the input signal based on the determined resonant frequency so as to generate the processed signal.
-
Patent Agency Ranking
公开(公告)号：WO2022034306A1
公开(公告)日：2022-02-17
申请号：PCT/GB2021/052063
申请日：2021-08-10
Inventor： THOMSEN, Axel , KING, Eric , DOY, Anthony , HOFF, Thomas , MELANSON, John
Abstract: This application relates to methods and apparatus for driving a transducer with switching drivers. A switching driver has first and second supply node for receiving supply voltages and includes an output bridge stage, a capacitor and a network of switches. The network of switches is operable in different switch states to provide different switching voltages to the output bridge stage. A controller is configured to control the switch state of the network of switches and a duty cycle of output switches of the output bridge stage based on an input signal to generate an output signal for driving the transducer.
-
公开(公告)号：WO2022034288A1
公开(公告)日：2022-02-17
申请号：PCT/GB2021/051967
申请日：2021-07-29
Inventor： DOY, Anthony S , KING, Eric
Abstract: The application describes a switched driver (401) for outputting a drive signal at an output node (402) to drive a load such as a transducer. The driver receives respective high-side and low-side voltages (VinH, VinL) defining an input voltage at first and second input nodes and has connections for first and second capacitors (403H, 403L). A network of switching paths is configured such that each of the first and second capacitors can be selectively charged to the input voltage, the first input node can be selectively coupled to a first node (N1) by a path that include or bypass the first capacitor, and the second input node can be selectively coupled to a second node (N2) by a path that includes or bypasses the second capacitor. The output node (402) can be switched between two switching voltages at the first or second nodes. The driver is selectively operable in different operating modes, where the switching voltages are different in each of said modes.
-
公开(公告)号：WO2021255415A1
公开(公告)日：2021-12-23
申请号：PCT/GB2021/051171
申请日：2021-05-14
Inventor： LESSO, John Paul
IPC: H04R1/10 , H04R5/033 , G10L25/06 , G10L25/93 , H04R1/1041 , H04R2460/13 , H04R29/004
Abstract: A method is used of detecting whether a device is being worn, when the device comprises a first transducer and a second transducer. It is determined when a signal detected by at least one of the first and second transducers represents speech. It is then determined when said speech contains speech of a first acoustic class and speech of a second acoustic class. A first correlation signal is generated, representing a correlation between signals generated by the first and second transducers during at least one period when said speech contains speech of the first acoustic class. A second correlation signal is generated, representing a correlation between signals generated by the first and second transducers during at least one period when said speech contains speech of the second acoustic class. It is then determined from the first correlation signal and the second correlation signal whether the device is being worn.
-
公开(公告)号：WO2021165637A1
公开(公告)日：2021-08-26
申请号：PCT/GB2021/050181
申请日：2021-01-26
Inventor： LESSO, John Paul
Abstract: An audio system receives an audio signal from a digital microphone, which has an analog-digital converter with a controllable sampling rate. In response to a determination that a predetermined trigger phrase is not detected in the decimated audio signal, the sampling rate of the analog-digital converter in the digital microphone is controlled such that the audio signal has a first sample rate. In response to a determination that the predetermined trigger phrase is detected in the decimated signal, the sampling rate of the analog-digital converter in the digital microphone is controlled such that the audio signal has a second sample rate higher than the first sample rate, and the audio signal is applied to a spoof detection circuit, to determine whether the received signal contains live speech or replayed speech.
-
公开(公告)号：WO2021123720A1
公开(公告)日：2021-06-24
申请号：PCT/GB2020/052788
申请日：2020-11-04
Inventor： LESSO, John Paul
IPC: H04R1/10 , H04R29/00 , G06F21/32 , A61B2562/0219 , A61B5/349 , A61B5/4803 , A61B5/6817 , A61B5/725 , H04R1/1016 , H04R1/1041 , H04R2460/03
Abstract: A sensor on an earpiece is used to attempt to detect a signal corresponding to a heartbeat. If a heartbeat is detected, it can be determined that the earpiece is being worn by a user. The sensor may be an acoustic transducer on a surface of the earpiece that is located within the wearer's ear canal, while the earpiece is being worn normally. The acoustic transducer may take the form of a microphone or loudspeaker used to detect acoustic signals.
-
-
-
-
-
-
-
-
-
Search Results
231
records
(took 0.058 seconds)
