公开(公告)号：WO2020146620A1

公开(公告)日：2020-07-16

申请号：PCT/US2020/012917

申请日：2020-01-09

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： HESTER, Richard ,  PAULETTI, Timothy, Patrick ,  CHEN, Suheng ,  AKOUR, Amneh, Mohammed ,  NATARAJAN, Nat, Maruthachalam ,  RANGARAJU, Jayanth

IPC: G05F1/575 ,  H02S40/30

Abstract: A controller circuit (102) for a PV sub-module (100) includes a power harvest controller circuit (104), a voltage limit controller circuit (106), a power mode control circuit (108), a multiplexer circuit (110), and a switching converter circuit (112). The power harvest controller circuit (104) has a first PV voltage input (114), a ceiling reference input (116), a floor reference input (118), and a first gate control output (120). The voltage limit controller circuit (106) has a first output voltage feedback input (122), a pulse width reference input (124), and a second gate control output (126). The power mode control circuit (108) has a second output voltage feedback input (128), a mode reference input (130), and a mode selection output (132). The multiplexer circuit (110) has a first gate control input (134), a second gate control input (136), a mode selection input (138), and a third gate control output (140). The switching converter circuit (112) has a second PV voltage input (142), a third gate control input (144), and a DC voltage output (146).

公开(公告)号：WO2020123937A1

公开(公告)日：2020-06-18

申请号：PCT/US2019/066222

申请日：2019-12-13

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： JONES, Jason A. T. ,  GOVINDARAJAN, Sriramakrishnan ,  MODY, Mihir Narendra ,  ISRAEL VIJAYPONRAJ, Kishon Vijay Abraham ,  COBB, Bradley Douglas ,  PRASAD, Sanand ,  SHURTZ, Gregory Raymond ,  AMBROSE, Martin Jeffrey ,  THAKUR, Jayant

IPC: G06F13/16 ,  G06F12/02

Abstract: An integrated circuit (120) includes an interconnect communication bus (130) and peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) (122, 124, 126, 128) coupled to the interconnect communication bus (130). Each PCI MFN-EP (122, 124, 126, 128) includes a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit. Each PCI function circuit includes another ATU and base address registers (BARs).

公开(公告)号：WO2020081709A1

公开(公告)日：2020-04-23

申请号：PCT/US2019/056571

申请日：2019-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： NEWMAN, Merril, Ray ,  LUO, Yiding ,  SMITH, David, Brian ,  DILLE, Michael, Richard ,  BEARDSWORTH, Matthew, Alan ,  MANLICK, Alan, R.

IPC: G06F3/0488 ,  H04M1/725

Abstract: A second touch area (314) is provided on a back side of a mobile phone (300) in a location such that an index finger can provide input when while the mobile phone (300) is being held in that one hand. A second hand is not required for the various types of input that are provided using the second touch area (314). This allows the mobile phone (300) to be used in single-handed operation in many circumstances.

公开(公告)号：WO2020037074A1

公开(公告)日：2020-02-20

申请号：PCT/US2019/046563

申请日：2019-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： HEREMAGALUR RAMAPRASAD, Bipin, Prasad ,  THOMPSON, David, Matthew ,  CHACHAD, Abhijeet, Ashok ,  ONG, Hung

IPC: G06F12/0862

Abstract: A system includes a CPU core (102), first and second memory caches (130, 155), and a memory controller subsystem (101). The memory controller subsystem (101) speculatively determines a hit or miss condition of a virtual address in the first memory cache (130) and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem (101) configures a status to a valid state. Responsive to receipt of a first indication from the CPU core (102) that no program instructions associated with the virtual address are needed, the memory controller subsystem (101) reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core (102) that a program instruction associated with the virtual address is needed, the memory controller subsystem (101) reconfigures the status back to a valid state.

公开(公告)号：WO2020023635A1

公开(公告)日：2020-01-30

申请号：PCT/US2019/043240

申请日：2019-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： WATERS, Deric Wayne

IPC: H01R25/00 ,  G05F1/00

Abstract: A circuit (100) including a first processing element (110) having a first output configured to couple to a voltage control circuit (112), a second output configured to couple to a gate terminal of a first transistor (116), and a third output configured to couple to a first node (118) and a control circuit (114). The control circuit (114) includes a second processing element having multiple outputs, a second transistor having a gate terminal configured to couple to one of the outputs of the second processing element, a first terminal configured to couple to a second node (134) and to a drain terminal of the first transistor (116), and a second terminal, and a third transistor having a gate terminal configured to couple to a second of the outputs of the second processing element, a first terminal configured to couple to a third node (132), and a second terminal.

公开(公告)号：WO2019213084A1

公开(公告)日：2019-11-07

申请号：PCT/US2019/029921

申请日：2019-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： BRANTLEY, Steven, G. ,  VASAN, Bharath, Karthik ,  PULIJALA, Srinivas, K. ,  SNOEIJ, Martijn

IPC: H03F3/45

Abstract: In examples, a system (100) includes a differential amplifier (110) coupled to a parasitic capacitor (119) positioned between a first node (120) and a first reference voltage source (Vrefl). Also, the system (100) includes a buffer amplifier (132) having an input terminal (133) and an output terminal (113). The input terminal (133) is coupled to the first node (120), and the output terminal (113) is coupled to a cancellation capacitor (136). Further, the system (100) includes a controlled current source (138) coupled to the first node (120) and the input terminal (133). Also, the controlled current source (138) is coupled to a second reference voltage source (Vref2). The system (100) includes a current sense circuit (134) coupled to the cancellation capacitor (136) and the second reference voltage source (Vref2).

公开(公告)号：WO2019126572A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/066933

申请日：2018-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： KIM, Sunglyong ,  SRIDHAR, Seetharaman ,  PENDHARKAR, Sameer

IPC: H01L27/06 ,  H01L29/861

Abstract: A lateral junction diode device (110) includes a substrate (105) having at least a semiconductor surface. A depletion-mode LDMOS device (130) is in the semiconductor surface including a source (131), a drain and a gate (133) above a gate dielectric (134), and a channel region (135) between the source (131) and the drain under the gate (133). A drift region (136a, 136b, 138) is between the channel region (135) and the drain. The drain also provides a cathode for the lateral junction diode device (110). An embedded diode (120) includes a second cathode (121) and an anode (122) that is shared with the device (110). The embedded diode (120) is junction isolated by an isolation region that comprises a well (123) coupled to a buried layer (124) located between the anode (122) and the source (131). The anode (122) and isolation region are directly connected to the gate (133), and the second cathode (121) is directly connected to the source (131).

公开(公告)号：WO2019108841A1

公开(公告)日：2019-06-06

申请号：PCT/US2018/063137

申请日：2018-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： SHENG, Zhongyan

IPC: G02B27/18 ,  G03B21/06 ,  H04N9/31

Abstract: A projector (100) includes a first prism (114) having a dichroic layer (118). A second prism (102) has a first spatial light modulator (104) on a first surface. First light (122) is directed through a second surface of the second prism (102) to the first spatial light modulator (104). The first spatial light modulator (104) is operable to modulate the first light (122) to provide modulated first light that is reflected off the second surface of the second prism (102) and the dichroic layer (118) to projection optics (120). A third prism (110) has a second spatial light modulator (112) on a first surface. Second light (124) is directed through a second surface of the third prism (110) to the second spatial light modulator (112). The second spatial light modulator (112) is operable to modulate the second light (124) to provide modulated second light that is reflected off the second surface of the third prism (110) and passes through the dichroic layer (118) to the projection optics (120).

公开(公告)号：WO2019084166A1

公开(公告)日：2019-05-02

申请号：PCT/US2018/057351

申请日：2018-10-24

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： COOK, Benjamin, Stassen ,  REVIER, Daniel, Lee

IPC: H01L23/28

Abstract: An encapsulated integrated circuit (100) includes an integrated circuit die (IC) (102). An encapsulation material (123) encapsulates the IC die (102). A phononic bandgap structure (121, 122) is included within the encapsulation material (123) that is configured to have a phononic bandgap with a frequency range approximately equal to a range of frequencies of thermal phonons (128) produced by the IC die (102) while the IC die (102) is operating.

公开(公告)号：WO2019071016A1

公开(公告)日：2019-04-11

申请号：PCT/US2018/054427

申请日：2018-10-04

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS INCORPORATED

Inventor： KODURI, Sreenivasan, K.

IPC: H01L23/48

Abstract: In a semiconductor packaging structure (100), a die (102) includes a bond pad (126) and a first metal layer structure (106, 107) disposed on the die (102). The first metal layer structure (106, 107) has a first width (109, 128). In the first metal layer structure, a first metal layer (107) is electrically coupled to the bond pad (124). The semiconductor packaging structure (100) also includes a first photosensitive material (104) around sides of the first metal layer structure (106, 107), and a second metal layer structure (112, 114) disposed over the first metal layer structure (106, 107) and over a portion of the first photosensitive material (104). The second metal layer structure (112, 114) is electrically coupled to the first metal layer structure (106, 107). The second metal layer structure (112, 114) has a second width (119), which is greater than the first width (109, 128). Also, the semiconductor packaging structure (100) includes a second photosensitive material (110) around sides of the second metal layer structure (112, 114).