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公开(公告)号：WO2020176587A1
公开(公告)日：2020-09-03
申请号：PCT/US2020/019838
申请日：2020-02-26
Applicant: INTEL CORPORATION
Inventor： STROBEL, Rainer , HEWAVITHANA, Thushara
IPC: H04L12/28
Abstract: An active cable node circuit associated with a hybrid fiber coax network is disclosed. The active cable node circuit comprises an uplink transceiver circuit configured to couple to an aggregation node circuit over a first coax cable link comprising coaxial cables and receive a set of downstream data signals from the aggregation node circuit. In some embodiments, the active cable node circuit further comprises one or more access transceiver circuits configured to provide the set of downstream data signals received at the uplink transceiver circuit or a processed version thereof, to one or more access circuits. In some embodiments, each of the one or more access transceiver circuits is configured to couple to the uplink transceiver circuit at a first end, and couple to a set of access circuits of the one or more access circuits at a second, different end, over a second coax cable link.
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2.发明申请
公开(公告)号：WO2020139450A1
公开(公告)日：2020-07-02
申请号：PCT/US2019/057873
申请日：2019-10-24
Applicant: INTEL CORPORATION
Inventor： KUTTNER, Franz
Abstract: High efficiency amplitude DACs and RFDACs employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.
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公开(公告)号：WO2020117317A1
公开(公告)日：2020-06-11
申请号：PCT/US2019/039154
申请日：2019-06-26
Applicant: INTEL CORPORATION
Inventor： GOICHBERG, Nathan
IPC: H04L5/14 , H04B1/54 , H03F3/62 , H04B1/58 , H04B3/36 , H04L12/28 , H04N7/10 , H04N21/61 , H04L5/00 , H04B1/00 , H04B1/48 , H04Q3/00
Abstract: A full duplex (FDX) trunk amplifier circuit configured to be coupled between a remote PHY (RPHY) circuit and one or more cable modems (CMs) is disclosed. The FDX trunk amplifier circuit comprises a trunk amplifier circuit comprising an amplifier circuit configured to convey a downstream transmission of a downstream data signal associated with the RPHY circuit in a FDX frequency band and an upstream transmission of an upstream data signal associated with the one or more CMs in the FDX frequency band, based on a direct current (DC) control signal. In some embodiments, the amplifier circuit is configured to convey the downstream transmission in the FDX frequency band and the upstream transmission in the FDX frequency band, at different instances, such that the downstream transmission in the FDX frequency band and the upstream transmission in the FDX frequency band do not overlap.
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公开(公告)号：WO2020068339A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/048488
申请日：2019-08-28
Applicant: INTEL CORPORATION
Inventor： ANGERER, Christoph , KLINKAN, Alexander , PLECHINGER, Peter
Abstract: A communication system using adaptive sample rate reduction (ASRR) is disclosed. The system includes a digital front end (DFE) and a radio frequency (RF) interface. The DFE is configured to receive a baseband signal, identify reduced performance parameters for the baseband signal, reduce a sampling rate for the baseband signal based on the reduced performance parameters and generate a digital interface signal using the reduced sampling rate. The RF interface is configured to generate an analog TX signal from the digital interface signal.
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公开(公告)号：WO2020033621A1
公开(公告)日：2020-02-13
申请号：PCT/US2019/045617
申请日：2019-08-08
Applicant: INTEL CORPORATION
Inventor： MOROZOV, Gregory V. , YE, Qiaoyang , CHATTERJEE, Debdeep
Abstract: An apparatus configured to be employed in an eNodeB associated with a machine type communication (MTC) system is disclosed. The apparatus comprises one or more processors configured to configure a mapping between cell-specific reference signal (CRS) antenna ports and demodulation reference signals (DMRS) antenna ports for an MTC physical downlink control channel (MPDCCH) associated with a UE, forming a CRS-to-DMRS antenna port mapping, to be provided to the UE, in order to enable the UE to perform coherent demodulation of the MPDCCH, based on CRS and DMRS. The one or more processors is further configured to generate a physical channel configuration signal comprising one or more mapping information parameters indicative of the CRS-to-DMRS antenna port mapping, in order to provide information on the CRS- to-DMRS antenna port mapping to the UE.
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Patent Agency Ranking
公开(公告)号：WO2020005441A1
公开(公告)日：2020-01-02
申请号：PCT/US2019/034317
申请日：2019-05-29
Applicant: INTEL CORPORATION
Inventor： DEGANI, Ofir , BANIN, Elan , BEN AMI, Eran
Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.
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公开(公告)号：WO2020005231A1
公开(公告)日：2020-01-02
申请号：PCT/US2018/039761
申请日：2018-06-27
Applicant: INTEL IP CORPORATION
Inventor： YU, Chuanzhao , ESCHBAUMER, Maximilian
Abstract: Embodiments relate to a transformer-based impedance matching network that may dynamically change its characteristic impedance by engaging different inductor branches on a primary side and optionally, on the secondary side. A primary side transformer circuit includes a primary inductor (311) and secondary inductor (321) configured to provide impedance matching over a first frequency band. One or more additional inductor branches (314A, 314B, are switchably coupled to either or both of the primary and secondary inductors to modify the impedance matching characteristics over additional operating frequencies. One or more LC filter branches (321, 322, 326, 327, 336, 330) can be included at the output of the secondary side to filter harmonic frequencies in each of the operating frequency bands.
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公开(公告)号：WO2019160633A1
公开(公告)日：2019-08-22
申请号：PCT/US2019/013600
申请日：2019-01-15
Applicant: INTEL CORPORATION
Inventor： THAKUR, Jayprakash
IPC: H01Q1/52
Abstract: An antenna isolation circuit configured to provide an isolation between two adjacent antennas in a wireless communication device is disclosed. The antenna isolation circuit comprises a partition line circuit comprising a conductive element configured to be placed between the two adjacent antennas; and a matching circuit having a first end and a second end. In some embodiments, the matching circuit is coupled to the partition line circuit at the first end and to a ground circuit at the second end. In some embodiments, the matching circuit is configured to provide an impedance.In some embodiments, a dimension of the conductive element and the impedance of the matching circuit are configured to result in an isolation between the two adjacent antennas.
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公开(公告)号：WO2019139706A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/064678
申请日：2018-12-10
Applicant: INTEL IP CORPORATION
Inventor： SUTSKOVER, Ilan , SEGEV, Eran , HENZLER, Stephan , BELITZER, Alexander
Abstract: A tracker circuit configured to provide a variable supply voltage to a power amplifier (PA) circuit is disclosed. The tracker circuit comprises a predefined state machine circuit comprising a plurality of states mapped in accordance with transitions associated with a predefined mapping scheme. In some embodiments, the plurality of states of the state machine circuit identify one or more operational modes associated with the tracker circuit, wherein the one or more operational modes comprises one or more voltage levels respectively associated therewith. In some embodiments, the one or more operational modes comprises at least two active operational modes. In some embodiments, a transition between the one or more operational modes of the tracker circuit is dictated by a decoding of a digital selection signal received from a digital communication interface associated therewith.
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10.发明申请
公开(公告)号：WO2019078934A1
公开(公告)日：2019-04-25
申请号：PCT/US2018/041119
申请日：2018-07-06
Applicant: INTEL IP CORPORATION
Inventor： POLA, Sudhir Shankar , BANSAL, Gaurav , GEORGE, Anish
Abstract: Techniques described herein may increase the efficiency of a network by ensuring that bearers, used in anonymous ( e.g. , emergency) calls are properly deactivated. A user equipment ("UE") may maintain an inactivity timer after an emergency call has ended, and may request that the network deactivate the bearer upon expiration of the inactivity timer, if the bearer is still active upon the expiration of the inactivity timer.
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